Package compatible device 10M0210M08...10M16 as assembly variant on request possible
SDRAM Memory up to 64Mb, 166MHzDual High Speed USB to 32 Mbyte (8Mbyte default)
USB 2.0 Multipurpose UART/FIFO IC
64Mb Quad SPI Flash
(FT2232H)
4 Kbit EEPROM Memory for FTDI configuration data
Micro USB Receptacle (communication and power)
SPI Flash - NOT INSTALLED (only special option)4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
16 Bit Analog to Digital Converter with 1 MSPS or 500 kSPS
2x SMA Female Connector
I/O interface: 23x GPIO
Power Supply:
5V
Minimum 1A
5V (from USB)
Dimension: 25 mm x 86.5 mm
Others:
Instrumentation Amplifier
Differential Amplifier
Operational Amplifier
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SMA Connector, J5...6
Amplifier, U12
Analog to Digital Converter, U6
Voltage Reference, U8
Voltage Regulator, U10 - U13 - U16
Switching Voltage Regulator, U11 - U4
SDRAM Memory, U2
Intel® MAX 10 FPGA, U1
SPI Flash Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UARTadapter/FIFO, U3
User LEDs, D2...9
4Kb EEPROM, U9
Configuration LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB2 ReceptacleUSB Connector, J9
1x14 pin header, J2 (Not assembled)
1x6 pin header, J4 (Not assembled)
Jumper, J3
1x14 pin header, J1 (Not assembled)
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Table_OV_IDS
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Initial delivery state of programmable devices on the module
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Storage device name
Content
Notes
Quad SPI Flash
N/A
Not
Programmed
populated
EEPROM
Programmed
FTDI configuration
SDRAM
Not Programmed
Configuration Signals
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Overview of Boot Mode, Reset, Enables.
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface
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(using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
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To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.
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FPGA Reconfigration can be triggered by pressing push button S1.
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Table_OV_RST
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Reset process.
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Signal
Push Button
Pin Header
Note
RESET
S1
J2
Connected to nCONFIG
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Table_OBP_IOs
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FPGA I/O Banks
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FPGA Bank
I/O Signal Count
Connected to
Notes
Bank 1A
7
1x14 Pin header, J1
AIN0...6
1
Jumper, J3
AIN7
Bank 1B
5
1x6 Pin header, J4
JTAG_EN, TDI, TDO, TMS, TCK
Bank 2
4
1x14 Pin header, J1
D2...5
5
ADC, U15
ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
1
12MHz Oscillator, U7
CLK12M
2
Amplifier, U12
nIAMP_A0, nIAMP_A1
Bank 3
22
SDRAM, U2
RAM_ADDR_CMD
Bank 5
9
1x14 Pin header, J2
DIO6...14
2
1x14 Pin header, J1
DIO0...1
1
D12_R
DIO12
Bank 6
16
SDRAM, U2
DQ0...15
2
SDRAM, U2
DQM0...1
1
D11_R
DIO11
Bank 8
8
User Red LEDs, D2...9
LED0...7
6
SPI Flash, U5
F_CS, F_CLK, F_DI, F_DO, nSTATUS, DEVCLRn
1
Red LED, D10
CONF_DONE
6
FTDI JTAG/UART Adapter, U3
BDBUS0...5
1
Push Button, S2
USER_BTN
Micro-
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USB Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interfacewith 166MHz clock frequency and CL3 CAS latency.
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Notes :
Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.
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Table_OBP_SDRAM
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SDRAM interface IOs and pins
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SDRAM I/O Signals
Signal Schematic Name
Connected to
Notes
Address inputs
A0 ... A13
bank 3
-
Bank address inputs
BA0 / BA1
bank 3
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Data input/output
DQ0 ... DQ15
bank 6
-
Data mask
DQM0 ... DQM1
bank 6
-
Clock
CLK
bank 3
-
Control Signals
CS
bank 3
Chip select
CKE
bank 3
Clock enable
RAS
bank 3
Row Address Strobe
CAS
bank 3
Column Address Strobe
WE
bank 3
Write Enable
FTDI FT2232H
The FTDI chip U3 converts signals from USB2 USB to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
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Table_OBP_FTDI
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FTDI chip interfaces and pins
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FTDI Chip U3 Pin
Signal Schematic Name
Connected to
Notes
ADBUS0
TCK
FPGA bank 1B, pin G2
JTAG interface
ADBUS1
TDI
FPGA bank 1B, pin F5
ADBUS2
TDO
FPGA bank 1B, pin F6
ADBUS3
TMS
FPGA bank 1B, pin G1
BDBUS0
BDBUS0
FPGA bank 8, pin A4
User configurable
BDBUS1
BDBUS1
FPGA bank 8, pin B4
User configurable
BDBUS2
BDBUS2
FPGA bank 8, pin B5
User configurable
BDBUS3
BDBUS3
FPGA bank 8, pin A6
User configurable
BDBUS4
BDBUS4
FPGA bank 8, pin B6
User configurable
BDBUS5
BDBUS5
FPGA bank 8, pin A7
User configurable
SPI Flash
BDBUS6
BDBUS6
FPGA bank 6, pin C11
BDBUS7
BDBUS7
FPGA bank 3, pin J7
BCBUS0
BCBUS0
FPGA bank 5, pin J9
BCBUS1
BCBUS1
FPGA bank 3, pin K5
BCBUS2
BCBUS2
FPGA bank 3, pin K5
BCBUS3
BCBUS3
FPGA bank 3, pin K5
BCBUS4
BCBUS4
FPGA bank 3, pin K5
SPI Flash
Optional SPI flash device maybe assembled in custom variants, normally it is not populatedOn-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
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Quad SPI Flash memory interface
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Signal Schematic Name
Connected to
Notes
F_CS
FPGA bank 8, pin B3
Chip select
F_CLK
FPGA bank 8, pin A3
Clock
F_DI
FPGA bank 8, pin A2
Data in / out
nSTATUS
FPGA bank 8, pin C4
Data in / out, configuration dual-purpose pin of FPGA
DEVCLRN
FPGA bank 8, pin B9
Data in / out, configuration dual-purpose pin of FPGA
F_DO
FPGA bank 8, pin B2
Data in / out
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The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.
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I2C EEPROM interface MIOs and pins
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Schematic
Connected to
Notes
EECS
FTDI U3, Pin EECS
EECLK
FTDI U3, Pin EECLK
EEDATA
FTDI U3, Pin EEDATA
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The boards with article nuber - TEI0016-03-08-C8A - are equipped with the Analog DevicesADC - ADAQ7988BCCZ - 16-bit 500kSPS, boards wit article number TEI0016-03-08-C8B are equipped with the Analog Devices ADC - ADAQ7980BCCZ - 16-bit 11MSPS.0MSPS.
The ADC can be distinguished via its part code:
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ADC converter interface and pins
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Pins
Connected to
Notes
IN+
U8, VOUTVREF_ADC
IN-
U12, VOUT
SDI
Bank 2, ADC_SDI
SDO
Bank 2, ADC_SDO
SCK
Bank 2, ADC_SCK
CNV
Bank 2, ADC_CNV
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Osillators
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Clock Source
Schematic Name
Frequency
Note
Microchip MEMS Oscillator, U7
CLK12M
12.00 MHz
Connected to FTDI FT2232 U3, pin 3.
Connected to FPGA SoC bank 2, pin H6.
Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
Power on-sequence
Power distribution
Voltage monitoring circuit
Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .
Power Supply
To power-up the module, power supply with minimum current capability of 1A is recommendedThe module is supplied from USB (optionally via unpopulated pin header).
Power Consumption
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Power Consumption
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FPGA
Typical Current
Intel MAX 10 10M08 FPGA SoCFPGA
TBD*
* TBD - To Be Determined
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There is no specific or special power-on sequence, just one single power source is needed. After power on, the green LED (D1) must will be on.