...
Additional assembly options are available for cost or performance optimization upon request.
Figure 1: TE022-02 block diagram.
Figure 2: TE0722-02 PCB top side.
Figure 3: TE0722-02 PCB bottom side.
Storage device name | Content | Notes |
---|---|---|
QSPI Flash | Empty |
Table 1: .
By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..
...
Bank | Type | Connector | I/O Signal Count | Voltage | Notes |
---|---|---|---|---|---|
34 | HR | P1 | 8 | 3.3 | P0 - P7 |
34 | HR | P2 | 8 | 3.3 | P24 - P31 |
34 | HR | P2 | 10, 5 LVDS pairs | 3.3 | |
34 | HR | J1 | 6 | 3.3 | X2A - X2F |
34 | HR | J2 | 2 | 3.3 | |
34 | HR | J3 | 4 | 3.3 | X1A - X1D |
35 | HR | P1 | 8, 4 LVDS pairs | 3.3 |
Table 3: .
JTAG access to the Xilinx ZYNQ XC7Z010 SoC is provided through J2 connector.
JTAG Signal | J2 Connector Pin |
---|---|
TCK | 4 |
TDI | 9 |
TDO | 10 |
TMS | 8 |
Table 4: .
MIO | Function | Connector Pin | Notes |
---|---|---|---|
0 | - | - | - |
1 | QSPI | - | SPI Flash-CS |
2 | QSPI | - | SPI Flash-DQ0 |
3 | QSPI | - | SPI Flash-DQ1 |
4 | QSPI | - | SPI Flash-DQ2 |
5 | QSPI | - | SPI Flash-DQ3 |
6 | QSPI | - | SPI Flash-SCK |
7 | GPIO | - | Green LED D2 |
8 | - | - | - |
9 | - | - | - |
28 | SD CARD | J8-5 | CLK |
29 | SD CARD | J8-3 | CMD |
30 | SD CARD | J8-7 | DAT0 |
31 | SD CARD | J8-8 | DAT1 |
32 | SD CARD | J8-1 | DAT2 |
33 | SD CARD | J8-2 | CD/DAT3 |
36 | I2C | - | SCL |
37 | I2C | - | SDA |
39 | GPIO | - | Si1143 INT pin |
49 | SD CARD | J8-G4 | Card detect switch |
Table 5: .
On-board I2C interface is provided via Zynq SoC's PS bank 501 pins MIO36 (SCL) and MIO37 (SDA). I2C addresses for on-board devices are listed in the table below:
I2C Device | Slave Address | Notes |
---|---|---|
Si1143-A11-GMR | 0x5A | Proximity and ambient light sensor. |
Table 6: .
LED | Color | Connected To | Description and Notes |
---|---|---|---|
D1 | Red | LED2, U4 | |
D2 | Green | MIO7, U1 | User controlled, default OFF (when PS7 has not been booted). |
D3 | Red | LED1, U4 | |
D4 | RGB | RGB_R, U1 RGB_G, U1 RGB_B, U1 | |
D5 | Red | LED3, U4 | |
D6 | Green | DONE, U1 | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL configuration is finished. |
Table 6: .
...
Power Input | Typical Current |
---|---|
3.3V | TBD* |
Table 7: Typical power consumption.
...
Power supply with minimum current capability of 1A for system startup is recommended.
Module Variant | Zynq SoC | ARM Cores | Operating Temperature | Temperature Range |
---|---|---|---|---|
TE0722-02I | XC7Z010-1CLG225I | –40°C to +85°C | Industrial | |
TE0722-02 | XC7Z010-1CLG225I | 0°C to +70°C | Commercial | |
TE0722-02-07S-1C | XC7Z007S-1CLG225C | 0°C to +70°C | Commercial |
Table 8: Module variants.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | -0.5 | 3.6 | V | Xilinx datasheet DS187, "Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics". |
Storage temperature | -40 | +85 | °C | Silicon Labs Si1141/42/43 datasheet. |
Table 9: Module absolute maximum ratings.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
Supply voltage | 1.14 | 3.465 | V | Xilinx datasheet DS187, "Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics". |
Table 10: Module recommended operating conditions.
Note |
---|
Assembly variants for higher storage temperature range are available on request. |
...
All dimensions are given in millimeters.
Figure 4: TE0722-02 physical dimensions.
...
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2015-10-23 | 02 | TE0722-02 | ||
01 |
|
Table 11: TE0722 module hardware revision history.
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
...
Date | Revision | Contributors | Description | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
| Jan Kumann | Initial document. |
Table 12: Document change history..
Include Page | ||||
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