Page History

Versions Compared

Key

This line was added.
This line was removed.
Formatting was changed.

...

Signals, Interfaces and Pins

...

I/O Signals

List of signals between PL banks and external connectors:

3.37

Bank	Type	Connector	I/O Signal Count	Voltage	Notes	0	JTAG	J2	4		JTAG interface.
34	HR	P1	8	3.3	P0 - P7
34	HR	P2	8	3.3	P24 - P31
34	HR	P2	10, 5 LVDS pairs	3.3
34	HR	J1	6	3.3	X2A - X2F
34	HR	J2	2	3.3
34	HR	J3	4	3.3	X1A - X1D
35	HR	P1	8, 4 LVDS pairs	3.3		501	MIO	J8		3.3

JTAG Interface

JTAG access to the Xilinx ZYNQ XC7Z010 SoC is provided through J2 connector.

...