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Table 3: Zynq SoC PL I/O signals overview
Zynq SoC PL/PS Banks
| Bank | Type | VCCIO | I/O's Count | Available on Connectors | Notes |
|---|---|---|---|---|---|
| 34 | HR | 3.3V | 41 | 38 | 38 user I/O's, 3 I/O's used for controlling the RGB LED D4. |
| 35 | HR | 3.3V | 8 | 8 | 8 single ended or 4 differential. |
| 500 | PS MIO | 3.3V | 7 | 0 | 6 MIO-pins used for QSPI flash memory interface, 1 MIO-pin connected to green LED D2. |
| 501 | PS MIO | 3.3V | 10 | 0 | 7 MIO-pins used for SD Card interface, 3 MIO-pins connected to light sensor U4. |
| 0 | Config | 3.3V | 5 | 0 | 4 I/O's are dedicated to JTAG interface, 'DONE'-signal is indicated by red LED D6. |
Table 4: General overview of Zynq SoC PL/PS banks
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The Zynq SoC board one reference clocking signal as system clock provided by on-board oscillator U8:
| Clock Source | Frequency | Clock Input Destination |
|---|---|---|
| SiTime SiT8008AI Oscillator, U8 | 33.333333 MHz | Zynq PS Bank 500, pin C7 |
Table 10: Clock sources overview
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Figure 4: Module power supply dependencies
Power Consumption
| Board Variant | FPGA | Design | Typical Power, 25°C ambient |
|---|---|---|---|
| TE0722-02I | XC7Z010-1CLG225I | Not configured | TBD* |
| TE0722-02 | XC7Z010-1CLG225C | Not configured | TBD* |
| TE0722-02-07S-1C | XC7Z007S-1CLG225C | Not configured | TBD* |
Table 12: Module power consumption
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