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In this section you must explain how to power on the board and run the Reference Design (test board) on the particular module. The main points must be mentioned are:

Overview of the board (point out the LEDs, Ethernets, Switches and etc on the board overview)
Explain Switches functionality
Explain user LEDs
Explain the UART connection
Refer to the Reference Design
Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guideline" .

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Table of Contents

Table of Contents

TEBF0808 with TE080x

Overview

Basic instructions to work with TEBF0808 and TE0808,TE0807 or TE0803.

Info
Functionality of buttons, DIP switches, LEDs depends on CPLD Firmware. Following description is only for newest firmware version, which is available on the download area

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title	Board Overview

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draw.io Diagram

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Number	Note	Letter	Note
1	S2- Reset Button	A	P1 - PMOD 3.3V I2C Bus
2	D7 - LED D7 Red (Usage: status) \|\| D6 - LED Green (Usage: status)	B	J9 - Audio Enclosure
3	S1 - Power Button	C	J26 - FAN1 12V
4	J25 - Power Jack J25, 2.1mm (optional 12V power input)	D	J17 - I2C (for optional module PLL access)
5	S5 - DIP Switch for Boot Mode and FMCVADJ	E	J6/15 - Firefly - GTH
6	J10 - Enclosure Pin header(Reset and Power Button, HD LED (Usage: status/user) and Power LED (Usage: status/user))	F	J31 - SATA
7	S4 - DIP Switch for CPLD access and power control	G	J21/22 - Firefly - loopback only
8	J12 - XMOD with green dot for Module JTAG and UART, XMOD LED D4 Red used for status information	H	P3 - PMOD 3.3V I2C Bus
9	J28 - XMOD for CPLD,FMC JTAG and Firmware ID over UART(need CPLD Firmware 7 or newer) , XMOD LED D4 Red used for status information	I	J34 - I2C Firefly
10	FPGA Done LED (location varies slightly on different module series )	J	J35 - FAN2 12V
11	J20 - ATX Power Connector (Main 12V and 5V Power supply), recommended power supply connector	K	J11 - PCIe (1x)
12	D1 - SFP LED Red (Usage: status/user)	L	B1 - Battery holder CR1220
13	D8 - SFP LED Green (Usage: status/user)	M	J30 - PJTAG
14	D9 - SFP LED Red (Usage: status/user)	N	J29 - CAN (same as J24)
15	D10 - SFP LED Green (Usage: status/user)	O	J5 - FMC HPC
16	J7 - ETH LED Yellow (Usage: status)	P	J19 - FAN3 5V
17	J7 - ETH LED Green/Orange (Usage: status)	Q	J24 - CAN (same as J29)
18	D4 - LED Green (Usage: status/user) \|\| D5 - LED Red (Usage: status/user)	R	J27 - SD
---	---	S	J8 - USB 3.0 (2x) Enclosure
---	---	T	J14 - SFP (2x)
---	---	U	J7 - USB 3.0 (2x), ETH (1x)
---	---	V	J13 - Displayport (1x)
---	---	W	P2 - PMOD 3.3V FPG IOs
---	---	W(b)	Bottom side: J16 - microSD

Power supply

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The input power supply must be mentioned. Add Link to overview picture with connector label.

Label	Designator	Power	Description
Overview - 12	J20	12V and 5V	Recommended power supply unit is PC power supply unit: DIP S4-4 can be switched OFF with this power supply configuration (CPLD firmware depended)
Overview - 4	J25	12V	Optional single 12V power supply: DIP S4-4 must be switched ON with this power supply

Current depends manly on design and cooling solution. Use Xilinx Power Estimator and/or Your Vivado Project to estimate min current. Minimum of 3A are recommanded for basic functionality.

DIP-Switches and Push Buttons

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Explain all DIP switches functionality. Add Link to overview picture with connector label.

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title	DIP Switches S4

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Overview 7	Default	Description
S4-1	OFF	SoC PUDC, ON (low - internal FPGA pull ups enabled), OFF (high - internal FPGA pull ups disabled)
S4-2	OFF	N.C.
S4-3	OFF	JTAGEN ON (CPLD access), OFF (FMC access)
S4-4	ON	Enable on board 5V permanently

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title	DIP Switches S5 (CPLD Firmware depended)

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Overview 5	Default	Description
S5-1	ON	ON(1), ON(2) - Default, boot from SD/microSD or SPI Flash if no SD is detected OFF(1), ON(2) - Boot from eMMC ON(1), OFF(2) - Boot mode PJTAG0 OFF(1), ON(2) -Boot mode main JTAG
S5-2	ON
S5-3	OFF	User Input to SoC over RGPIO interface
S5-4	OFF	VADJ OFF(1.8V), ON(1.2V)

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title	Buttons (CPLD Firmware depended)

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Overview 1;3;6

Default

Description

S1

High

Negative Reset Button, alternative Enclosure over J10-7/J10-5

Press appr. 1sec for PS Soft Reset
Press appr 3 sec for PS POR Reset

S2

High

Negative Power Button, alternative Enclosure over J10-6/J10-8

Press appr. 1sec for PS Soft Reset
Press appr 3 sec for PS POR Reset

LEDs

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Explain all user LEDs functionality and connections. Add Link to overview picture with connector label.

LEDs used different Blink Sequence to indicate all state:

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title	LED Sequencing (CPLD Firmware depended)

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Blink Sequence	Frequence	Note
******** (slow blinking)	~0,7 Hz	continuous blinking, like SFP LEDs or Enclosure HD LED when board is powered down
******** (fast blinking)	~5,8 Hz	continuous blinking, like D6 LED or Enclosure Power LED when board is powered down
*****ooo	~0,7 Hz, duty cycle 5/8	5 times fast blink with a break
****oooo	~0,7 Hz, duty cycle 4/8	4 times fast blink with a break
***ooooo	~0,7 Hz, duty cycle 3/8	3 times fast blink with a break
**oooooo	~0,7 Hz, duty cycle 2/8	2 times fast blink with a break
*ooooooo	~0,7 Hz, duty cycle 1/8	1 times fast blink with a break
ON	---	LED ON
OFF	---	LED OFF

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title	Carrier LEDs (CPLD Firmware depended)

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Label

Designator

Color

Usage

Description

Overview - 2

D7

Red

status

Priority	Description	Blink sequencing
1	PS POR Reset pressed long time (or whole system is powered off)	ON
2	PS Soft Reset pressed short time	OFF
3	SD Boot	*ooooooo
4	QSPI Boot	**oooooo
5	eMMC Boot	***ooooo
6	PJTAG Boot	****oooo
7	JTAG Boot	*****ooo
8	Error	******** (fast blinking)

Overview - 2

D6

Green

status

Priority	Description	Blink sequencing
1	Power OFF	******** (fast blinking)
2	PG_LPD low	*****ooo
3	PG_FPD low	****oooo
4	PG_PL low	***ooooo
5	PG_DDR low or PG_PSGT low or PG_PLL low or PG_GT_L low or PG_GT_R low	**oooooo
6	POK_1V8 low or POK_FMC low or perihpery_pg low or (Main Power State Machine Ready and FMC Sanity check low)	*ooooooo
7	Main Power State Machine Ready	OFF
8	ERROR some power failed, see XMOD LEDs	ON

Overview - 6

J10 Power LED

Blue (symbol light bulb)

status/user

Priority	Description	Blink sequencing
1	power button pressed long time forced power down	******** (fast blinking)
2	Main Power State Machine Idle and Power of State	******** (slow blinking)
3	power button pressed short time power to power on/off	*****ooo
4	PS reset button pressed long time	****oooo
5	PS reset button pressed short time	***ooooo
6	power down sequencing is running	**oooooo
7	whole system hold into reset	*ooooooo
8	MIO40	User Defined

Overview - 6

J10 HD LED

Red (symbol drive)

status/user

Priority	Description	Blink sequencing
1	PS Init is low	******** (fast blinking)
2	PS Error High	*****ooo
3	PS Error Status High	****oooo
4	SOC Done low	***ooooo
5	SC0	User Defined

Overview - 8

XMOD1 D4

Red

status

Priority	XMOD Button	Description	Blink sequencing
1	Pressed	Main Power State Machine Ready, but FMC Sanity check failed	******** (fast blinking)
2	Pressed	PS State Machine PS LPD ON/OFF	*ooooooo
3	Pressed	PS State Machine PS FPD ON/OFF	**oooooo
4	Pressed	PS State Machine PS DDR,GT,PLL ON/OFF	***ooooo
5	Pressed	PL State Machine PL and PL GT ON/OFF	****oooo
6	Pressed	PS Init low	ON
1	Unpressed	Main Power State Machine ATX ON/OFF	*ooooooo
2	Unpressed	Main Power State Machine 5V ON/OFF	**oooooo
3	Unpressed	Main Power State Machine Module ON/OFF	***ooooo
4	Unpressed	Main Power State Machine 1.8V ON/OFF	****oooo
5	Unpressed	Main Power State Machine 3.3V and VADJ ON/OFF	*****ooo
6	Unpressed	Main Power State Machine Wait Ready ON/OFF	******** (fast blinking)
7	Unpressed	PS Init low	ON
x	Pressed/Unpressed	all fine	OFF

Overview - 9

XMOD2 D4

Red

status/user

Priority	Description	Blink sequencing
1	Power On Reset	******** (slow blinking)
2	PS Init high	******** (fast blinking)
3	SC17	User Defined

Overview - 12

SFP D1

Red

status/user

Priority	Description	Blink sequencing
1	Power On Reset	******** (slow blinking)
2	PS Init high	******** (fast blinking)
3	RGPIO(0), when RGPIO Enabled over FPGA	User Defined
4	--	OFF

Overview - 13

SFP D8

Green

status/user

Priority	Description	Blink sequencing
1	Power On Reset	******** (slow blinking)
2	PS Init high	******** (fast blinking)
3	RGPIO(1), when RGPIO Enabled over FPGA	User Defined
4	--	OFF

Overview - 14

SFP D9

Red

status/user

Priority	Description	Blink sequencing
1	Power On Reset	******** (slow blinking)
2	PS Init high	******** (fast blinking)
3	RGPIO(2), when RGPIO Enabled over FPGA	User Defined
4	--	OFF

Overview - 15

SFP D10

Green

status/user

Priority	Description	Blink sequencing
1	Power On Reset	******** (slow blinking)
2	PS Init high	******** (fast blinking)
3	RGPIO(3), when RGPIO Enabled over FPGA	User Defined
4	--	OFF

Overview - 16

ETH J7

Yellow

status

Priority	Description	Blink sequencing
1	Power On Reset	******** (slow blinking)
2	PS Init high	******** (fast blinking)
3	ETH PHY LED	(not PHY_LED0)

Overview - 17

ETH J7

Green/Orange

status

Priority	Description	Blink sequencing
1	Power On Reset	******** (slow blinking)
2	PS Init high	******** (fast blinking)
3	ETH PHY LED	(PHY_LED1)

Overview - 18

D4

Green

status/user

Priority	Description	Blink sequencing
1	1.8V disabled, inter CPLD RGPIO is disabled	******** (fast blinking)
2	1.8V enabled, inter CPLD RGPIO is disabled	*****ooo
3	Power On Reset	****oooo
4	USB Reset	***ooooo
5	RGPIO(4), when RGPIO Enabled over FPGA	User Defined
6	all fine	*ooooooo

Overview - 18

D5

Red

status/user

Priority	Description	Blink sequencing
1	1.8V disabled, inter CPLD RGPIO is disabled	******** (fast blinking)
2	1.8V enabled, inter CPLD RGPIO is disabled	*****ooo
3	Power On Reset	****oooo
4	PCie Reset	***ooooo
5	RGPIO(4), when RGPIO Enabled over FPGA	User Defined
6	all fine	*ooooooo

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title	Module LEDs

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Label	Designator	Color	Connected to	Description
Overview - 10	D1	Red	DONE signal (PS Configuration Bank 503)	This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly.

JTAG/UART

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Explain JTAG or UART connection . Add Link to overview picture with connector label.

Label	Designator	Description
Overview - 8	J12	SoC JTAG/UART over USB, UART Speed depends on design, normally 15200 XMOD with Xilinx Licence (green dot)
Overview - 9	J28	CPLD or FMC JTAG over USB XMOD without Xilinx Licence Press Button to see Firmware ID over UART (need CPLD Firmware 7 or newer), UART Speed 115200

DIP Switch on bouth XMOD JTAG adapters must be set like on the following table.

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title	XMOD JTAG DIP Switch. Attention: Never changes the default setting

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XMOD DIP Switch	Setting
1	ON
2	OFF
3	OFF
4	OFF

For more information refer to TE0790.

CPLD Firmware

Firmware Update Instruction and CPLD description are available on TEBF0808 CPLD Firmware. Source code of the firmware is available on the download area of the TEBF0808.

Firmware Versions and some statistics can be displayed over second XMOD:

Included since CPLD Firmware Update to REV07
UART Speed is 115200
Press XMOD Button to see output, otherwise RX/TX are loop backed

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title	CPLD Firmware ID

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anchor	Table_CPLD_FIRM
title	CPLD Firmware and Statistic over UART

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Type	Description
TE0808-x_CPLD-REV07	CPLD Firmware Version
MP	Main Power State, Note: Only correct, if 1.8V is powered on First Number indicates 1.8V Power state(1-ON) Second Number indicates Main State Machine: 0:IDLE (Power OFF) 1:ATX ON/OFF 2:V5 ON/OFF 3:Module Power ON/OFF → (Different domains over LED visible) 4:1.8V ON/OFF 5:Periphery ON/OFF 6: Wait Ready (Power Ok, SoC on Reset) 7. Ready (Power/SoC OK)
PIN	PS Init, when Power Reset released First Number current PS-INIT (Inverted) Second Number PSINIT counter
PEE	PS ERROR, when Power Reset released First Number current PS-ERROR Second Number ERROR counter
PES	PS ERROR Status, when Power Reset released First Number current PS-ERROR Status Second Number ERROR Status counter
PSR	PS Soft Reset(also high, PS Power On Rese is active) First Number current PS-Soft Reset Second Number PS-Soft Reset counter
PHR	PS Power On Reset First Number current PS- Power On Reset Second Number PS- Power On Reset counter
POR	Main Power On Reset First Number current Main- Power On Reset Second Number Main Power On Reset counter
USB	USB Reset First Number current USB Reset Second Number USB reset counter
PCI	PCIe Reset First Number current PCIe Reset Second Number PCIe reset counter

Reference Designs

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In this Section you must refer to the Reference Design (Test board) for the particular module.

For Example: TE0728 Reference Designs

Link to different Reference Designs (Descriptions and Download)

It's recommended to use prebuilt Boot.bin and image.ub of newest Starterkit Reference Design for first test. Basic Steps:

Power Supply over ATX, optional 12V power jack
Download Reference Design
Copy Boot.bin and image.ub on SD
Connect USB to XMOD with Green Dot
Open Putty
Set Boot Mode to SD, set DIP S5-1 and S5-2 to ON (Overview 5) and inserted SD with Design on SD Slot (Overview R)
Press Power Button on Enclosure or on Carrier (Overview 3)
For more detailed check Reference Design description

Notes

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In this Section you must refer to the Resources Page for the particular module.

For Example: TE0728 Resources

Module and Carrier are also as starter kit available:

Links to all documentation and download resources:

Trenz Electronic Documentation

Versions Compared

Old Version 16

New Version 17

Key

TEBF0808 with TE080x

Overview

Power supply

DIP-Switches and Push Buttons

LEDs

JTAG/UART

CPLD Firmware

Reference Designs

Notes