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Quick Start

The most Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

The "normal" Vivado project will be generated in the subfolder "/vivado/" after executing scripts (YouTube: TE0720 Project Creation).

There are several options to create the Vivado project from the project delivery. These options are described in Vivado Projects.

If you use our prepared batch files for project creation do the following steps:

1. open "design_basic_settings.cmd/.sh" with text editor and set correct vivado path and board part number. How select the correct board part number is described on TE Board Part Files
2. run "vivado_create_project_guimode.cmd/.sh"

See  Reference Design: Getting Started for more details.

Since 2018.3 special "Module Selection Guide" is included into "_create_win_setup.cmd" and "_create_linux_setup.sh"

• Execute "_create_win_setup.cmd" or "_create_linux_setup.sh"
• Select "Module Selection Guide" (press "0" and Enter)
• Follow instructions

For manuell configuration or addition command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS. If you use our prepared batch files for project creation do the following steps:

1. open "design_basic_settings.cmd/.sh" with text editor and set correct vivado path and board part number (this will be also done automatically with the "Module Selection Guide" ). How select the correct board part number is described on TE Board Part Files
2. run "vivado_create_project_guimode.cmd/.sh"

See  Reference Design: Getting Started for more details.

If you need our Board If you need our Board Part files only, see Board Part Installation.

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Zip Project Delivery

Zip Name Description

Last supported Release

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• • Important Note: QSPI Programming need special FSBL on 20182017.2 4 or higher for all Zynq/ZynqMP. Special programming FSBL will be provided on 2018.2 all newer reference designs
  • Linux OS only: HSI software generation failed.
    • Reason: start "gmake" failed, alias is not set on Ubuntu
    • Workaround: "sudo ln -s /usr/bin/make /usr/bin/gmake" to generate alias or use  SDK GUI to generate applications and boot files.
  • Linux OS only: Function, which used external programs.
    • Reason: Currently only set correctly for Win OS.
    • Workaround: Change TCL scripts program path manually.

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Command Files

Command files will be generated with "_create_win_setup.cmd" on Windows  and "_create_linux_setup.sh" on Linux OS. Linux shell files are currently not available for this release.

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TE-TCL-Extentsions

Design Environment: Usage

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• Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
  (optional) Install Xilinx Vivado LabTools (Lab Edition)Configure
• Automatically configuration of the reference-designs (only with 2018.3 scripts and newer):
  • Run "_create_win_setup.cmd" or "_create_linux_setup.sh"
    
    • select "module selection guide" and follow instructions.
      • "design_basic_settings.cmd" will be configured over this menu
• Manual Configure the reference-design:
  1. Open “design_basic_settings.cmd” with design:
  1. Open “design_basic_settings.cmd” with a text-editor:
      a. Set correct Xilinx Environment:
          @set XILDIR=C:/Xilinx
          @set VIVADO_VERSION=2018.23
          Program settings will be search in :
          %XILDIR%/VIVADO/%VIVADO_VERSION%/
          %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
          %XILDIR%/SDK/%VIVADO_VERSION%/
          Example directory: c:/Xilinx/Vivado/2018.23/
          Attention: Scripts are supported only with predefined Vivado Version!
      b. Set the correct module part-number:
          @set PARTNUMBER=x
          You found the available Module Numbers in <design_name>/board_files/<board_series>_board_files.csv
      c. Set Application name (for programming with batch-files only):
          @set SWAPP=NA
          NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
         <app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
• Create all prebuilt files in one step:
  2. Run “design_run_project_batchmode.cmd”
• (optional to Step 2) Create all prebuilt files in single steps:
  3. Run “vivado_create_project_guimode.cmd”:
      A Vivado Project will be create and open  in ./vivado
  4. Type “TE::hw_build_design” on Vivado TCL-Console:
      Run Synthese, Implement and create Bitfile and optional MCSfile
  5. Type “TE::sw_run_hsi” on Vivado TCL-Console:
      Create all Software Applications from <design_name>/sw_lib/apps_list.csv
  6. (optional to Step 5) Type “TE::sw_run_sdk” on Vivado TCL-Console:
      Create a SDK Project in <design_name>/workspace/sdk
      Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps

• Programming FPGA or Flash Memory with prebuilt Files:
  7. Connect your Hardware-Modul with PC via JTAG.
  With Batch-file:
  8. (optional) Zynq-Devices Flash Programming (*.bin):
      Run “program_flash_binfile.cmd”
  9. (optional) FPGA-Device Flash Programming (*.mcs):
      Run “program_flash_mcsfile.cmd”
  10. (optional) FPGA-Device Programming (*.bit):
        Run “program_fpga_bitfile.cmd”
  With Vivado/Labtools TCL-Console:
  11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado  or LabTools
  12. (optional) Zynq-Devices Flash Programming (*.bin):
        Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
        Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  13. (optional) FPGA-Device Flash Programming (*.mcs):
        Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
        Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  14. (optional) FPGA-Device Programming (*.bit):
        Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
        Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

Basic Design Settings

Project Configuration

1. Unzip project files
2. Rename basefolder (basefolder name is used as project name)
3. Edit design_basic_settings.cmd
   1. Select the correct Xilinx Program path (See: Windows Command Files → design_basic_settings.cmd)
   2. Select the correct board part number for your PCB  (See: Windows Command Files → design_basic_settings.cmd)
   3. Other settings are optional  (See: Windows Command Files → design_basic_settings.cmd)
4. Excecute vivado_create_project_guimode.cmd or vivado_create_project_batchmode.cmd to generate a vivado project with the predefined Block Design from the Block Design folder
5. Open Vivado with vivado_open_existing_project_guimode.cmd (if you use vivado_create_project_guimode.cmd on step 4, you didn't need this)
6. Open the Block Design and create your own design inside this Block Design.
7. Backup your Block Design as tcl-script: Type "TE::hw_blockdesign_export_tcl" on Vivado Tcl Console. The old one will be overwritten.
8. Build your Design...

Initialise TE-scripts on Vivado/LabTools

Initialise TE-scripts on Vivado/LabTools

• Variant 1 (recommended):
  • Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
• Variant 2:
  • Create your own Initialisation Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push
    • Type Name ex.: Init Scripts
    • Press Enter
    • Select Run command and insert:
      
      • for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
      • for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
        
    • Press Enter
    • A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
      
• Variant 3:
  • Reinitialise Script on Vivado TCL-Console:
    • Type: source
• Variant 1 (recommended):
  • Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
• Variant 2:
  • Create your own Initialisation Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push
    • Type Name ex.: Init Scripts
    • Press Enter
    • Select Run command and insert:
      for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace " ../scripts/reinitialise_all.tcl"
    • for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
      
    • Press Enter
    • A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
      
• Variant 3:
  • Reinitialise Script on Vivado TCL-Console:
    • Type: source ../scripts/reinitialise_all.tcl
      
• • • 
      

Use Use predefined TE-Script functions

• Variant 1 (recommended):
  • Typ function on Vivado TCL Console, ex.: TE::help
  • TE::help
    
    • Show all predefined TE-Script functions.
  • TE:<functionname> -help 
    
    • Show short description of this function.
    • Attention: If -help argument is set, all other args will be ignored. 
• Variant 2:
  • Create your own function Button on the Vivado GUI:
    • Tools → Customize Commands → Customize Commands...
    • Push +
    • Type Name ex.: Run SDK
      
    • Press Enter
      
    • Select Run command and insert function:
      • Variante 1 (no Vivado request window for args):
        • insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
      • Variant 2 (Vivado request window for args):
        • insert function, ex.:TE::sw_program_zynq
        • Press Define Args...
        • For every arg:
          
          • Push
          • Typ Name, Comment, Default Value and set optional
          • Press Enter
            
          • Example for args:
          • • Push
            • Index, Key Name, -swapp,
            • Push
            • Appname, Arg, hello_world,
              
             
    • Press Enter
    • A new Button is shown on the Vivado Gui.

Hardware Design

Board Part Files

See also More details see TE Board Part Files

Structure Board Parts

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• board.xml
  
• part0_pins.xml
• preset.xml
• picture.jpg or picture.png

Board Part

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or Design Extension

Board Part Carrier Extensions are a TCL-Scripts, which can be sourced in Vivado Block Design. Thy are used usable with TE-Scripts only. It contains additional settings of PS-System for settings or special carrier-board , if no special Board part file exists.

Board Part Carrier Extensions  are located on subfolder "board_files/carrier_extension/" with file name *_preset.tcl.

design changes.

Use Reference Designs or Vivado TCL-Console(TE-Script extensions, see Initialise TE-scripts on Vivado/LabTools): TE::hw_blockdesign_create_bd -help to create PS with full settings. Or source the TCL file manually direct after "Run Block Automation" 

Possible:

• Board Part PS settings  are located on subfolder "board_files/preset_extension/" with file name *_preset.tcl.
• Design modiflications are located on subfolder "board_files/bd_mod/" with file name *_bd.tcl.
  

Board Part CSV Description

Board Part csv file is used for TE-Scripts only.

Block Design Conventions

• Only one Block-Design per project is supported

• Recommended BD-Names (currently importend for some TE-Scripts):
   

  Name	Description
  zsys	Idendify project as Zynq Project with processor system (longer name with *zsys* are supported too)
  zusys	Idendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too)
  msys	Idendify project as Microblaze Project with processor system (longer name with *msys* are supported too)
  fsys	Idendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)

   
  

• Create Basic Block Design with PS Board-Part Preset and Carrier-Board extended settings (only if subfolder carrier_extension with tcl files is available), use TE::hw_blockdesign_create_bd -help
  

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• All *.xdc from <design_name>/constrains/ are load into the vivado project on project creation.
  Attention: If subfolder <design_name>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module!

• Recommended XDC-Names (used for Vivado XDC-options):

  Property	Name part	Description
  Set Processing Order	*_e_*	set to early
  	*_l_*	set to late
  		set to normal
  Set Used In	*_s_*	used in synthese only
  	*_i_*	used in implement only
  		used in both, synthese and implement

  
  

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• Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
  It will be saved as *_bd.tcl
  Attention: If subfolder <design_name>/block_design/<board_file_shortname> or  <design_name>/block_design/PCB Revision> is defined, it will be saved there!
                  Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>

Microblaze Firmeware

• Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance>or <design_name>/firmware/<BD hierarchie>/<Microblaze IP Instance>.
• For MCS-Core use MCS IP Instance Name. This name must use *mcs* or *syscontrol* in the name.

Software Design

HSI: Generate predefined software from libraries

• To generate predefinde predefined software from libraries, run "TE::sw_run_hsi" on Vivado TCL-Console
• All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticlyautomaticity
• Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app

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To modifiy current board part csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.

See Chapter Board Part Files for more information.

User defined Settings

Vivado settings:

Chapter Board Part Files for more information.

User defined Settings

Vivado settings:

Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name>/settings/project_settings.tcl". This file will be loaded automatically on project creation.

Script settings:

Vivado Project settings (corresponding TCL-Commands) can be Additional script settings (only some predefined  variables) can be  saved as a user defined file "<design_name>/settings/projectdevelopment_settings.tcl". This file will be loaded automatically on project creationscript initialisation.

Script Design settings:

Additional script settings (only some predefined  variables) can be  saved as a user defined file "<design_name>/settings/developmentdesign_settings.tcl". This file will be loaded automatically on script initialisation.

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