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• Only one Block-Design per project is supported
• Recommended BD-Names (currently importend for some TE-Scripts):
   

   

   

  Name	Description
  zsys	Idendify project as Zynq Project with processor system (longer name with *zsys* are supported too)
  zusys	Idendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too)
  msys	Idendify project as Microblaze Project with processor system (longer name with *msys* are supported too)
  fsys	Idendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)

   

   

   
• Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
  It will be saved as *_bd.tcl
  Attention: Is If subfolder <design_name>/block_design/<board_file_shortname> is defined, it will be saved there!
                  Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>

XDC Conventions

• All *.xdc from <design_name>/constrains/ are load into the vivado project on project creation.
  Attention: If subfolder <design_name>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module!
• Recommended XDC-Names (used for Vivado XDC-options):

   

   

  Property	Name part	Description
  Set Processing Order	*_e_*	set to early
  	*_l_*	set to late
  		set to normal
  Set Used In	*_s_*	used in synthese only
  	*_i_*	used in implement only
  		used in both, synthese and implement

   

   

   

Checklist / Troubleshoot

1. Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
2. Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
3. Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
4. Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
5. Did you have the newest reference design build version? Maybe it's only a bug from a older version.
6. Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
7. If nothing helps, send a mail to trenz support (support(at)trenz-electronic.de) with subject line "[TE-Reference Designs] ",  the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)

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