Page History

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Changes

#3 Changed DCDC EN5311QI (U24, U25, U26) to MPM3834CGPA and adapted power circuit.

Type: Schematic Change

Reason: EOL of Component.

Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#1 Changed DCDC (U23) from EN6347QI to MPM3860GQW-Z and adapted power circuit.

Type: Schematic Change

Reason: EOL of Component.

Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#4 Changed load switch (Q1) from TPS27082LDDCR to MP5077GG-Z and adapted circuit.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#1 Added power supervisor (U4) for voltage rail VIN handling.

Type: Schematic Change

Reason: Power handling improvement.

Impact: Power supply starts only if voltage rail VIN is in adequate voltage range.

#8 Changed ferrid bead BKP0603HS121-T (L2...L7, L10...L13) to MPZ0603S121HT000.

Type: Schematic Change

Reason: EOL of Component.

Impact: None.

#8 Changed power sequencing.

Type: Schematic Change

Reason: Follow AMD recommendation.

Impact: Voltage rails start in other order. Voltage supervisor (U4) enables 1V voltage rail (DCDC U23) via signal EN_Module. 1V DCDC (U23) enables 1.8V voltage rail (DCDC U25) via signal PG_1V0. 1.8V DCDC (U25) enables 2.5V (DCDC U24) and DDR_VDD (DCDC U26) voltage rails via signal PG_1V8. Voltage rail 3.3V (load switch Q1) is logical AND-enabled via power good signal PG_2V5_3V3 from voltage rail 2.5V DCDC (U24) and DDR_VDD DCDC (U26) via diode (D4) and CPLD (U6) signal EN_3V3 via diode (D5).

#10 Added additional decoupling capacitors C166...C179.

Type: Schematic Change

Reason: Improve decoupling.

Impact: None.

#10 Added level shifter (U9) and capacitors (C185, C186) to separate power domains for signal FPGA_IO. Added fallback resistor (R91).

Type: Schematic Change

Reason: Improve power domain handling for signal FPGA_IO.

Impact: None.

#9 Added optional diode (D3) between signal nets "PROG_B"and "INIT".

Type: Schematic Change

Reason: Optionally, keep FPGA in reset while signal "PROG_B" is low during initial power-up.

Impact: None.

#5 Added diode (D3) between U21 pin 3 net nRST_in and voltage rail 3.3V.

Type: Schematic Change

Reason: Protect manual reset pin.

Impact: None.

#1 Connected exposed pad for SDIO port expander (U15) to GND.

Type: Schematic Change

Reason: Improve thermal situation.

Impact: None.

#1 Changed power net name from 1.5V to DDR_VDD.

Type: Schematic Change

Reason: Improve name handling.

Impact: None.

#1 Pulled-up board revision signal (FPGA U2 pin H17) and updated board revision documentation.

Type: Schematic Change

Reason: Update revision information.

Impact: None. Firmware reflects it but custom firmware needs to be updated by customer.

#19 Added revision history, block and power diagram. Updated page count and order. 

Type: Documentation Update

Reason: Documentation improvement.

Impact: None.

#11 Changed fiducials to standard fiducial type.

Type: Schematic Change

Reason: Use standard fiducials.

Impact: None.

#10 Removed serial number S/N.

Type: Schematic Change

Reason: EOL of Component.

Impact: None.

#17 Added testpoints TP1...TP41.

Type: PCB Change

Reason: Improve signal monitoring.

Impact: None.

#19 Added serial number box print on bottom overlay.

Type: PCB Change

Reason: Required for manufacturing.

Impact: None.

Method of Identification

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