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- Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
(optional) Install Xilinx Vivado LabTools (Lab Edition) - Configure the reference-design:
1. Open “design_basic_settings.cmd” with a text-editor:
a. Set correct Xilinx Environment:
@set XILDIR=C:/Xilinx
@set VIVADO_VERSION=2015.4
Program settings will be search in :
%XILDIR%/VIVADO/%VIVADO_VERSION%/
%XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
%XILDIR%/SDK/%VIVADO_VERSION%/
Example directory: c:/Xilinx/Vivado/2015.4/
Attention: Scripts are supported only with predefined Vivado Version!
b. Set the correct module part-number:
@set PARTNUMBER=x
You found the available Module Numbers in ./board_files/<board_series>_board_files.csv
c. Set Application name (for programming with batch-files only):
@set SWAPP=NA
NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
<app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> - Create all prebuilt files in one step:
2. Run “design_run_project_batchmode.cmd” - (optional to Step 2) Create all prebuilt files in single steps:
3. Run “vivado_create_project_guimode.cmd”:
A Vivado Project will be create and open in ./vivado
4. Type “TE::hw_build_design” on Vivado TCL-Console:
Run Synthese, Implement and create Bitfile and optional MCSfile
5. Type “TE::sw_run_hsi” on Vivado TCL-Console:
Create all Software Applications from ./sw_lib/apps_list.csv
6. (optional to Step 5) Type “TE::sw_run_sdk” on Vivado TCL-Console:
Create a SDK Project in <design_name>/workspace/sdk
Include Hardwaredefinition, Bitfile annd local Software libraries from in <design_name>/sw_lib Programming FPGA or Flash Memory with prebuilt Files:
7. Connect your Hardware-Modul with PC via JTAG.
With Batch-file:
8. (optional) Zynq-Devices Flash Programming (*.bin):
Run “program_flash_binfile.cmd”
9. (optional) FPGA-Device Flash Programming (*.mcs):
Run “program_flash_mcsfile.cmd”
10. (optional) FPGA-Device Programming (*.bit):
Run “program_fpga_bitfile.cmd”
With Vivado/Labtools TCL-Console:
11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado or LabTools
12. (optional) Zynq-Devices Flash Programming (*.bin):
Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
13. (optional) FPGA-Device Flash Programming (*.mcs):
Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
14. (optional) FPGA-Device Programming (*.bit):
Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
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- Variant 1 (recommended):
- Typ function on Vivado TCL Console, ex.: TE::help
- TE::help
- Show all predefined TE-Script functions.
- TE:<functionname> -help
- Show short description of this function.
- Attention: If -help argument is set, all other args will be ignored.
- Variant 2:
- Create your own function Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push +
- Type Name ex.: Run SDK
- Press Enter
- Select Run command and insert function:
- Variante 1 (no Vivado request window for args):
- insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
- Variant 2 (Vivado request window for args):
- insert function, ex.:TE::sw_program_zynq
- Press Define Args...
- For every arg:
- Push
- Typ Name, Comment, Default Value and set optional
- Press Enter
- Example for args:
- Push
- Index, Key Name, -swapp,
- Push
- Appname, Arg, hello_world,
- Push
- Push
- Variante 1 (no Vivado request window for args):
- Press Enter
- A new Button is shown on the Vivado Gui.
- Create your own function Button on the Vivado GUI:
Hardware Design
Block Design Conventions
- Only one Block-Design per project is supported
- Recommended BD-Names (currently importend for some TE-Scripts):
Name Description zsys Idendify project as Zynq Project with processor system (longer name with *zsys* are supported too) zusys Idendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too) msys Idendify project as Microblaze Project with processor system (longer name with *msys* are supported too) fsys Idendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too) - Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
It will be saved as *_bd.tcl
Attention: Is subfolder <design_name>/block_design/<board_file_shortname> defined, it will be saved there!
Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>
Checklist / Troubleshoot
- Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
- Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
- Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
- Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
- If nothing helps, send a mail to trenz support (support(at)trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)
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