Page History

Overview

CPLD Device with designator U14: LCMX02-1200HC

Feature Summary

• Power Management
  • VADJ Configuration via DIP-Switch or I2C
• Reset Management
• Boot Mode Controller
• FPGA UART routing
• I2C to GPIO

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

Dip Switch

^*Note that JTAGMODE signal does not work for the PCB REV06 or older. But it will work for PCB REV07 or newer, which is not produced yet.

**Pin names in the schematic of board are CM1,CM0 and JTAGEN. These Names on the board (labels) are M2,M1 and ENJTAG respectively.

JTAG

In normal mode JTAG is routed directly to the module. JTAGEN set the CPLD of the carrier board into the chain for firmware update. Set S3-C (ENJTAG) to OFF to get access to the CPLD of the carrier board. In normal mode  JTAG is routed directly to FPGA.

^{*Note that JTAGMODE is not connected to the B2B connector for PCB REV06 or older. This pin will be connected to the B2B connector for next PCB revisions. (PCB REV07 or later)}

PCB REV06

In the PCB REV06 or older the JTAGMODE signal is not connected to the JTAGEN of the CPLD of the module. Therefore in the PCB REV06 or older the CPLD of the module can not be programmed.

PCB REV07 or newer

A special firmware is generated for accessing to the CPLD of TE0715 module, because for accessing to the CPLD of TE0715 the JTAG port must be routed to special pins same as NOSEQ pin. Therefore in PCB the CPLD firmware REV06 or later CM0 is used to select the accessing to the CPLD of TE0715 module. JTAGMODE signal set the CPLD of the module into the chain for firmware update. 

FMC JTAG

FMC JTAG can be set into the chain, if the special generated firmware is programmed into the CPLD of the carrier board. 

PCB REV06

PCB REV07 or newer

Power

EN1 is set to logical one . As default EN_FMC is set to logical one. This pin can be controlled by I2C on I2C Mode. PG_C2M is set to logical one or is controlled by I2C on I2C Mode.

To set the EM_FMC signal to zero → i2cset -y 0 0x30 0x03 0x00

EN5335QI PowerSoC VADJ

The EN5335QI is a Power System on a Chip (PowerSoC). It is specifically designed to meet the precise voltage and fasr transient requirements of present and future high performance, low-power processor, DSP, FPGA, memory boards and system level applications in a distributed power architecture. The output variable voltage can be adjusted by three signals VS0, VS1 and VS2. The VSx signals are connected to VID0, VID1 and VID2 signals of the CPLD of the carrier board.  

VADJ for PCB REV06 or newer

The output voltage VADJ can be adjusted with both S4 dip switch (S4-A, S4-B and S4-C) and I2C interface. If the all S4 dip switchs set to OFF the variable voltage can be selected via I2C interface. 

If the S4-A,B,C set to OFF , the output voltage of the regulator can be controlled via I2C interface. In this case GPIO_output[2:0] will control the voltage.

i2cset -y 0 0x30 0x00 0x00

i2cset -y 0 0x30 0x00 0x01

i2cset -y 0 0x30 0x00 0x02

i2cset -y 0 0x30 0x00 0x03

i2cset -y 0 0x30 0x00 0x04

i2cset -y 0 0x30 0x00 0x05

i2cset -y 0 0x30 0x00 0x06

VADJ for PCB REV05 or older

The firmware REV06 does not support the PCB REV05 or older , because there is not S4 dip switch on the board. Therefore the VID0, VID1 and VID2 signals can not be controlled for adjusting the desired voltage. 

Push buttons

Reset

The module can be reset via S2 push button as external reset. (active low)

PGOOD

The PGOOD signal can be set or reset via S4-D (CM2) dip switch as shown:

NOSEQ

The NOSEQ signal can be set or reset via S3-A (CM1) dip switch as shown:

MODE

This signal can be set or reset by SD_DETECT signal, which is connected to the interna switch of the SD card connector. This signal is used to select the desired boot mode as shown:

Boot Mode

Boot mode can be selected via two PGOOD and MODE signals. 

I2C to GPIO

I2C to GPIO is a subsystem in firmware of CPLD that provides an i2c interface that writes received data to GPIO_output 8 bit registers or reads  8 bit GPIO_input registers and send read data to i2c bus. 

I2C bus is connected to MIO10 ( SCL signal) and MIO11 (SDA signal). MIO10 to MIO15 are direct connection between CPLD of TE0701 and FPGA on the module through B2B connector. If in FPGA design exists  no i2c interface for MIO10 and MIO11, this block will be unused. More information about MIO10 to MIO15 are shown in the following table for whole Trenz Electronic 4x5 modules and TE0701 carrier board:

I2C to GPIO registers access methods

I2C to GPIO subsystem has 4 output and 4 input 8 bit registers. These registers can be written or read in linux or FSBL code as shown in the following tables:

i2cget -y 0 0x30 0x00

iic_read8(0x30,0x00,&data)

i2cget -y 0 0x30 0x01

iic_read8(0x30,0x01,&data)

i2cget -y 0 0x30 0x02

iic_read8(0x30,0x02,&data)

i2cget -y 0 0x30 0x03

iic_read8(0x30,0x03,&data)

i2cset -y 0 0x30 0x00 <data>

iic_write8(0x30,0x00,data)

i2cset -y 0 0x30 0x01 <data>

iic_write8(0x30,0x01,data)

i2cset -y 0 0x30 0x02 <data>

iic_write8(0x30,0x02,data)

i2cset -y 0 0x30 0x03 <data>

iic_write8(0x30,0x03,data)

I2C to GPIO registers

FMC I2C

To convert the 3 wire spilt I2C interface to two wire I2C interface the following code is used in the firmware:

FMC_SDA       <= '0' when Y5='0' else 'Z';
Y1            <= FMC_SDA;

FMC_SCL       <= Y0 and PON;

In this case FMC_SCL and FMC_SDA are connected to the FMC card. On the other hand Y0 as I2C SCL pin , Y1 as I2C SDA input and Y5 as I2C SDA output are connected to the CPLD and B2B connector.

UART

It is two UART interfaces for Microchip modules and only one UART interface for AMD modules.  For Microchip modules the UART interface can be multiplexed between UART0 (HSS console) and UART1 (Linux console) via S1 user push button. By booting in the beginning UART0 is connected as default to the UART interface. The user can swith to UART1 (Linux console) by pressing the S1 push button any time and vice versa. For Microchip modules the *.jed file is special and the CPLD chip of the carrier board must be reprogrammed for this purpose.

draw.io Diagram
border true diagramName TE0701_CPLD_UART_Blockdiagramm simpleViewer false width links auto tbstyle top lbox true diagramWidth 1071 height 621 revision 2

LED

Appx. A: Change History and Legal Notices

Revision Changes

• Changes REV05 to REV06:

  •  UART interface UART0 only for Microchip modules added

  • S1 is used for multiplexing UART0 and UART1 for Microchip modules.

  • LEDs and PHY_LEDs function is changed.

  • I2C interface with 0x30 address  is added. It is connected to MIO10 (SCL) and MIO11 (SDA).

  • I2C interface with 0x22 address for HDMI chip is removed. This interface was connected to HDMI_SCL and HDMI_SDA.

  • The generic parameters JTAG_TOPOLOGY, PCB_REVISION, CPLD_REVISION_MAJOR, CPLD_REVISION_MINOR and MICROCHIP_MODULE are added.

  • PGOOD is used as boot mode selector pin in addition to MODE pin (SD_DETECT). In addition to SD card /QSPI boot modes JTAG and eMMC boot modes can be selected.

  • PGOOD, NOSEQ can be set or reset via CM2 (S4-D) and CM1 (S3-A) respectively.

  • The FMC_VADJ voltage can be changed via S4-A,B,C dip switches. This variable voltage can be changed via I2C interface too, if S4-A,B,C dip switches are OFF.

  • The CPLD of module can be programmed for REV07 or newer versions. (Next PCB revisions) JTAGMODE pin is added. JTAGMODE signal can be controlled with CM0 (S3-B) for PCB REV07 or newer versions.

  • RGPIO is not used more.

  • FMC JTAG Port is added.

  • Connecting PGOOD to CM2 to use as boot mode pin selector

  • JTAG timing correction 
    

• Changes Older Revisions to REV05:

  • Power Management

    • three VADJ Control Modi (REV06+ S4 Control, REV05- S3 Control and I2C Control)

  • Reset Management

    • only little changes

  • RGPIO Interface to FPGA

    • RGPIO support

  • LED

    • new Order and accessible by RGPIO

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Legal Notices