Page History

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Type: Schematic Change

Reason: Improve name handlingnaming.

Impact: None.

#6 Changed power sequencing.

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Reason: Follow AMD and Texas Instruments recommendation.

Impact: Voltage Check that the new voltage rails start in other order fits your requirements. Voltage supervisor (U4) enables 1V voltage rail (DCDC U23) via signal EN_Module. 1V DCDC (U23) enables 1.8V voltage rail (DCDC U25) via signal PG_1V0. 1.8V DCDC (U25) enables 2.5V (DCDC U24) and DDR_VDD (DCDC U26) voltage rails via signal PG_1V8. Voltage rail 3.3V (load switch Q1) is logical AND-enabled via power good signal PG_2V5_3V3 from voltage rail 2.5V DCDC (U24) and DDR_VDD DCDC (U26) via diode (D4) and CPLD (U6) signal EN_3V3 via diode (D5).

#7 Added bidirectional level shifter (U7) and capacitors (C185, C186) to separate power domains for signal FPGA_IO. Added fallback resistor (R91).

Type: Schematic Change

Reason: Improve power domain handling for signal FPGA_IO.

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Reason: Use standard fiducials.

Impact: None.

#17 Removed

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track-it traceability pad S/N.

Type: Schematic Change

Reason: EOL of Component.

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Type: PCB Change

Reason: Improve signal monitoringtesting.

Impact: None.

#19 Added serial number box print on bottom overlay.

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