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Type or FileVersion
Vivado Design Suite2016.2
Trenz Project Scripts2016.2.0507
Trenz <board_series>_board_files.csv1.2
Trenz apps_list.csv

1.9

Trenz zip_ignore_list.csv1.0


Directory structure

File or DirectoryTypeDescription
<design_name>base directoryBase directory with predefined batch files (*.cmd) to generate or open VIVADO-Project
<design_name>/block_design/sourceScript to generate Block Design in Vivado (*_bd.tcl). (optional) Some board part designs used subfolder <board_file_shortname>  with Board Part specific Block Design (*_bd.tcl).
<design_name>/board_files/sourceLocal board part files repository and a list of available board part files  (<board_series>_board_files.csv)
<design_name>/board_files/carrier_extensionsource(Optional) Additional TCL-Scripts to extend Board Part PS-Preset with carrier board specific settings.
<design_name>/constraints/sourceProject constrains (*.xdc). Some board part designs used subfolder <board_file_shortname>  with additional constrains (*.xdc)
<design_name>/doc/sourceDocumentation
<design_name>/hdl/sourceHDL-File and XCI-Files. Advanced usage only!
<design_name>/firmware/sourceELF-File Location for MicroBlaze Firmware.  Additional sub folder is used for MicroBlaze identification.
<design_name>/ip_lib/sourceLocal Vivado IP repository
<design_name>/misc/source(Optional) Directory with additional sources
<design_name>/prebuilt/boot_images/prebuiltDirectory with prebuilt boot images (*.bin) and configuration files (*.bif)  for zynq and configured hardware files (*.bit and *.mcs) for micoblaze included in sub-folders: default or <board_file_shortname>/<app_name>
<design_name>/prebuilt/hardware/prebuiltDirectory with prebuilt hardware sources (*.bit, *hdf, *.mcs) and reports included in subfolders: default or <board_file_shortname>
<design_name>/prebuilt/software/prebuilt(Optional) Directory with prebuilt software sources (*.elf) included in subfolders: default or <board_file_shortname>/<app_name>
<design_name>/prebuilt/os/prebuilt(Optional) Directory with predefined OS images included in subfolders  <os_name>/<board_file_shortname> or <os_name>/default
<design_name>/scripts/sourceTCL scripts to build a project
<design_name>/settings/source(Optional) Additional design settings: zip_ignore_list.csv, vivado project settings, SDSOC settings
<design_name>/software/source(Optional) Directory with additional software
<design_name>/os/source(Optional) Directory with additional os sources in in subfolders  <os_name>
<design_name>/sw_lib/source(Optional) Directory with local SDK/HSI software IP repository and a list of available software (apps_list.csv)
<design_name>/v_log/generated(Temporary) Directory with vivado log files (used only when Vivado is started with predefined command files (*.cmd) from base folder otherwise this logs will be writen into the vivado working directory)
<design_name>/vivado/work, generated(Temporary) Working directory where Vivado project is created. Vivado project file is <design_name>.xpr
<design_name>/vivado_lab/work, generated(Optional/Temporary) Working directory where Vivado LabTools is created. LabTools project file is <design_name>.lpr
<design_name>/workspace/hsiwork, generated(Optional/Temporary) Directory where hsi project is created
<design_name>/workspace/sdkwork, generated(Optional) Directory where sdk project is created
<design_name>/sdsocwork, generated(Optional) Directory where SDSOC project is created
<design_name>/backup/generated(Optional) Directory for project backups

 

Windows Command Files

File NameDescription
Design + Settings
design_basic_settings.cmd

Settings for the other *.cmd files. Following Settings are avaliable:

  • General Settings:
    • (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing
    • (optional) ZIP_PATH: Set Path to installed Zip-Program. Currently 7-Zip are supported. IUsed for predefined TCL-function to Backup project.
    • (optional) ENABLE_SDSOC: Enable SDSOC Setting. Currently only for some reference project as beta version!
  • Xilinx Setting:
    • XILDIR: Set Xilinx installation path (Default: c:\Xilinx).
    • VIVADO_VERSION: Current Vivado/LabTool/SDK Version (Example:2015.4). Don't change Vivado Version.
      • Xilinx Software will be searched in:

      • VIVADO (optional for project creation and programming): %XILDIR%\Vivado\%VIVADO_VERSION%\

      • SDK (optional for software projects and programming): %XILDIR%\SDK\%VIVADO_VERSION%\

      • LabTools (optional for programming only): %XILDIR%\Vivado_Lab\%VIVADO_VERSION%\

      • SDSOC (optional): %XILDIR%\SDSOC\%VIVADO_VERSION%\
  • Board Setting:
    • PARTNUMBER: Set Board part number of the project which should be created
      • Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list)
      • Used for project creation and programming
      • To create empty project without board part, used PARTNUMBER=-1 (use GUI to create your project. No block design tcl-file should be in /block_design)
      • Example TE0726 Module :
      • USE ID                 |USE PRODID                      |Use Boardname                                                |Use Shortname
        PARTNUMBER=1|PARTNUMBER=te0726-01 |PARTNUMBER=trenz.biz:te0726-01:part0:1.0 |PARTNUMBER=TE0726-01
  • Programming Settings(program*file.cmd):
    • SWAPP: Select Software App, which should be configured.
      • Use the folder name of the <design_name>/prebuilt/boot_image/<partname>/* subfolder. The *bin,*.mcs or *.bit from this folder will be used.
      • If you will configure the raw *.bit or *.mcs  *.bin  from the <design_name>/prebuilt/hardware/<partname>/ folder, use @set SWAPP=NA or @set SWAPP="".
      • Example: SWAPP=hello_world   → used the file from prebuilt/boot_image/<partname>/hello_world
                        SWAPP=NA                → used the file from <design_name>/prebuilt/boot_image/<partname>/
    • PROGRAM_ROOT_FOLDER_FILE: If you want to program design file from the rootfolder <design_name>, set to 1

      • Attention: it should be only one *.bit, *.msc or *.bin file in the root folder.

design_clear_design_folders.cmd(optional)  Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files
design_run_project_batchmode.cmd

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/hsi/" directory with related documents before Projekt will created.

Hardware Design

vivado_create_project_guimode.cmd

Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process.

Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Projekt will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_create_project_batchmode.cmd

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Projekt will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_open_existing_project_guimode.cmdOpens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables.
Software Design
sdk_create_prebuilt_project_guimode.cmd(optional) Create SDK project with hardware definition file from prebuild folder. It used the *.hdf from: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd".
Programming
program_flash_binfile.cmd(optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK  "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd".
program_flash_mcsfile.cmd(optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
program_fpga_bitfile.cmd(optional)  Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
labtools_open_project_guimode.cmd

(optional)  Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".

...

exporttclnomigcontentsnovalidatemodtclsvntxt <arg>]  boardpartonlyhelp]Export Block Design to project folder <design_name>/block_design/ . Old *bd.tcl will be overwritten!builddesignexportprebuilt
NameOptionsDescription (Default Configuration)
TE::help Display currently available functions. Important: Use only displayed functions and no functions from sub-namespaces 
Hardware Design
TE::hw_blockdesign_create_bd[-bd_name] [-msys_local_mem] [-msys_ecc] [-msys_cache] [-msys_debug_module] [-msys_axi_periph] [-msys_axi_intc] [-msys_clk] [-help]

Create new Block-Design with initial Setting for PS, for predefined bd_names:
fsys→Fabric Only, msys→Microblaze, zsys→7Series Zynq, zusys→UltraScale+ Zynq

Typ TE::hw_blockdesign_create_bd -help for more information

TE::hw_blockdesign_export_tcl[-no_mig_contents] [-no_validate] [-mod_tcl] [-svntxt <arg>]  [-board_part_only] [-help]Export Block Design to project folder <design_name>/block_design/ . Old *bd.tcl will be overwritten!
TE::hw_build_design[-export_prebuilt] [-export_prebuiltexport_prebuilt_only] [-help]Run Synthese, Implement, and generate Bit-file, optional MCS-file and some report files
Software Design
TE::sw_run_hsi[-run_only] [-prebuilt_hdf <arg>] [-no_hsi] [-no_bif] [-no_bin] [-no_bitmcs] [-clear] [-help]

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
Copy the Hardware Defintition file to the working directory:<design_name>/workspace/hsi
Run HSI in <design_name>/workspace/hsi for all Programes listed in <design_name>/sw_lib/apps_list.csv
If HSI is finished, BIF-GEN and BIN-Gen are running for these Apps in the prepuilt folders <design_name>/prebuilt/...
You can deactivate different steps with following args :

  • -no_hsi  : *.elf filesgeneration is disabled
  • -no_bif   : *.bif files generation is disabled
  • -no_bin  : *.bin files generation is disabled
  • -no_bitmcs: *.bit and *.mcs file (with software design) is disabled
TE::sw_run_sdk[-open_only] [-update_hdf_only] [-prebuilt_hdf <arg>] [-clear] [-help]

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
Copy the Hardware Defintition file to the working directory:<design_name>/workspace/sdk
Start SDK GUI in this workspace

Programming
TE::pr_init_hardware_manager[-help]Open Hardwaremanager, autoconnect target device and initialise flash memory with configuration from *_board_files.csv.
TE::pr_program_jtag_bitfile[-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_bitfile] [-help]

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only).
Programming Bitfile from <design_name>/prebuilt/hardware/<board_file_shortname> to the fpga device.
If "-used_basefolder_bitfile" is set, the Bitfile (*.bit)  from the base folder (<design_name>) is used instead of the prebuilts. Attention: Take only one Bitfile in the basefolder!

(MicroBlaze only) If "-swapp" is set, the Bitfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

TE::pr_program_flash_binfile[-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-force_hw_manager] [-used_basefolder_binfile] [-help]

Attention: For Zynq Systems only!
Program the Bootbin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> to the fpga device.
Appname is selected with: -swapp <app_name>
After programming device reboot from memory will be done.
Default SDK Programmer is used, if not available LabTools Programmer is used.
If "-used_basefolder_binfile" is set, the Binfile (*.bin)  from the base folder (<design_name>) is used instead of the prebuilts. Attention: Take only one Binfile in the basefolder!

TE::pr_program_flash_mcsfile[-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_mcsfile] [-help]

Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only).
Initialise flash memory with configuration from *_board_files.csv
Programming  MCSfile from <design_name>/prebuilt/hardware/<board_file_shortname> to the Flash Device.
After programming device reboot from memory will be done.
If "-used_basefolder_binfile" is set, the MCSfile (*.mcs)  from the base folder (<design_name>) is used instead of  the prebuilts. Attention: Take only one MCSfile in the basefolder!

(MicroBlaze only) If "-swapp" is set, the MCSfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

Utilities
TE::util_zip_project[-save_all] [-remove_prebuilt] [-manual_filename <arg>] [-help]

Make a Backup from your Project in <design_name>/backup/

Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported.

Beta Test (Advanced usage only!)
TE::ADV::beta_util_sdsoc_project[-check_only] [-start_sdsoc_only] [-help]

Create SDSOC-Workspace. Currently only on some Reference-Designs available. Run [-check_only] option to check SDSOC ready state.

TE::ADV::beta_hw_remove_board_part[-permanent] [-help]Reconfigure Vivado project as project without board part. Generate XDC-File from board part IO definitions and change ip board part properties. No all IPs are supported.
TE::ADV::beta_hw_export_rtl_ip\[-help\]Save IPs used on rtl designs as  *.xci in  <design_name>hdl/xci. If sub folder  <board_file_shortname> is defined this will be saved there.

...

  • Variant 1 (recommended):
    • Typ function on Vivado TCL Console, ex.: TE::help
    • TE::help
      • Show all predefined TE-Script functions.
    • TE:<functionname> -help 
      • Show short description of this function.
      • Attention: If -help argument is set, all other args will be ignored. 
  • Variant 2:
    • Create your own function Button on the Vivado GUI:
      • Tools → Customize Commands → Customize Commands...
      • Push +
      • Type Name ex.: Run SDK
      • Press Enter
      • Select Run command and insert function:
        • Variante 1 (no Vivado request window for args):
          • insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
        • Variant 2 (Vivado request window for args):
          • insert function, ex.:TE::sw_program_zynq
          • Press Define Args...
          • For every arg:
            • Push (plus)
            • Typ Name, Comment, Default Value and set optional
            • Press Enter
            • Example for args:
              • Push (plus)
              • Index, Key Name, -swapp, (tick)
              • Push (plus)
              • Appname, Arg, hello_world, (tick)
               
      • Press Enter
      • A new Button is shown on the Vivado Gui.


Hardware Design

Block Design Conventions

  • Only one Block-Design per project is supported

  • Recommended BD-Names (currently importend for some TE-Scripts):
     

    NameDescription
    zsysIdendify project as Zynq Project with processor system (longer name with *zsys* are supported too)
    zusysIdendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too)
    msysIdendify project as Microblaze Project with processor system (longer name with *msys* are supported too)
    fsysIdendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)

      

XDC Conventions

  • All *.xdc from <design_name>/constrains/ are load into the vivado project on project creation.
    Attention: If subfolder <design_name>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module!

  • Recommended XDC-Names (used for Vivado XDC-options):

    PropertyName partDescription
    Set Processing Order*_e_*
    		set to early
    *_l_*set to late
     set to normal
    Set Used In*_s_*used in synthese only
    *_i_*used in implement only
     used in both, synthese and implement

Backup Block Design as TCL-File

  • Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
    It will be saved as *_bd.tcl
    Attention: If subfolder <design_name>/block_design/<board_file_shortname> is defined, it will be saved there!
                    Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>

 

Microblaze Firmeware

  • Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance>.

 

Software Design

HSI: Generate predefined software from libraries

  • To generate predefinde software from libraries, run "TE::sw_run_hsi" on Vivado TCL-Console
  • All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticly
  • Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app

SDK: Create user software project

  • To start SDK project, run "TE::sw_run_sdk" on Vivado TCL-Console
    Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps
  • To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type  "TE::sw_run_sdk -prebuilt_hdf <board_number>" on Vivado-TCL-Console
  •  To open an existing SDK-project without update HDF-Data, type  "TE::sw_run_sdk -open_only" on Vivado-TCL-Console

Advanced Usage

Attention not all features of the TE-Scripts are supported in the advanced usage!

User defined board part csv file

...

"<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32

Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build.

 

Board Part Files

Structure Board Parts

Board Parts located on subfolder "board_files", with the name of the special board. Revisions are splitt in the subfolder of the board part <boardpart_name><version>

Every Version of a Board Parts consists of four files:

  • board.xml
  • part0_pins.xml
  • preset.xml
  • picture.jpg
Board Part Carrier Extension
Board Part CSV Description

Board Part csv file is used for TE-Scripts only.

 

 

NameDescriptionValue
IDID to identify the board variant of the module series, used in TE-ScriptsNumber, should be unique in csv list
PRODIDProduct ID, currently not used in TE-ScriptsProduct Name
PARTNAMEFPGA Part Name, used in Vivado and TE-ScriptsPart Name, which is available in Vivado, ex. xc7z045ffg900-2
BOARDNAMEBoard Part Name, used in Vivado and TE-ScriptsBoard Part Name or "NA", which is available in Vivado, NA is not defined to run without boardpart, ex. trenz.biz:te0782-02-45:part0:1.0
SHORTNAMESubdirectory name, used for multi board projects to get correct sources and save prebuilt dataName, should be unique in csv list
ZYNQFLASHTYPFlash typ used  for programming Zynq-Devices via SDK-Programming Tools (program_flash)"qspi_single" or "NA", NA is not defined
FPGAFLASHTYPFlash typ used  for programming Devices via Vivado/LabTools

"<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32

Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build.

 



Block Design Conventions

  • Only one Block-Design per project is supported

  • Recommended BD-Names (currently importend for some TE-Scripts):
     

    NameDescription
    zsysIdendify project as Zynq Project with processor system (longer name with *zsys* are supported too)
    zusysIdendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too)
    msysIdendify project as Microblaze Project with processor system (longer name with *msys* are supported too)
    fsysIdendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)

     

  • Create Basic Block Design with PS Board-Part Preset and Carrier-Board extended settings (only if subfolder carrier_extension with tcl files is available), use TE::hw_blockdesign_create_bd -help


XDC Conventions

  • All *.xdc from <design_name>/constrains/ are load into the vivado project on project creation.
    Attention: If subfolder <design_name>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module!

  • Recommended XDC-Names (used for Vivado XDC-options):

    PropertyName partDescription
    Set Processing Order*_e_*
    		set to early
    *_l_*set to late
     set to normal
    Set Used In*_s_*used in synthese only
    *_i_*used in implement only
     used in both, synthese and implement

Backup Block Design as TCL-File

  • Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
    It will be saved as *_bd.tcl
    Attention: If subfolder <design_name>/block_design/<board_file_shortname> is defined, it will be saved there!
                    Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>

 

Microblaze Firmeware

  • Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance>.

 

Software Design

HSI: Generate predefined software from libraries

  • To generate predefinde software from libraries, run "TE::sw_run_hsi" on Vivado TCL-Console
  • All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticly
  • Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app


SDK: Create user software project

  • To start SDK project, run "TE::sw_run_sdk" on Vivado TCL-Console
    Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps
  • To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type  "TE::sw_run_sdk -prebuilt_hdf <board_number>" on Vivado-TCL-Console
  •  To open an existing SDK-project without update HDF-Data, type  "TE::sw_run_sdk -open_only" on Vivado-TCL-Console


Advanced Usage

Attention not all features of the TE-Scripts are supported in the advanced usage!

User defined board part csv file

To modifiy current board part To modifiy current csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.

See Chapter Board Part Files for more information.

User defined Settings

Vivado settings:

...