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91	UP	3.3V	JTAG input from FTDI chip
M_TDI	in	94	UP	3.3V	JTAG input from FTDI chip
M_TDO	out	95	UP	3.3V	JTAG output to FTDI chip
M_TMS	in	90	UP	3.3V	JTAG input from FTDI chip
CM0	in	99	UP	3.3V	DIP switch S3-B
CM1	in	1	UP	3.3V	DIP switch S3-A
CM2	in	51	UP	3.3V	REV06+ only: DIP Switch S4-D
EN_FMC	out	31	NONE	3.3V	VADJ and 3V3V_FMC Power on
EN1	out	24	UP	3.3V	Power enable pin for CPLD of module
FMC_PRSNT	in	28	UP	3.3V	FMC card present pin (Zero if not present)
FMC_SCL	out	10	UP	3.3V	FMC I2C clock signal
FMC_SDA	inout	8	UP	3.3V	FMC I2C data signal
FMC_TCK	out	4	DOWN	3.3V	FMC port JTAG signal
FMC_TDI	out	12	DOWN	3.3V	FMC port JTAG signal
FMC_TDO	in	9	DOWN	3.3V	FMC port JTAG signal
FMC_TMS	out	7	DOWN	3.3V	FMC port JTAG signal
HDMI_SCL	inout	47	UP	3.3V	HDMI chip I2C clock signal / used also for I2C FMC control
HDMI_SDA	inout	45	UP	3.3V	HDMI chip I2C data signal / used also for I2C FMC control
HDMI_SPDIF	out	15	NONE	3.3V	Audio input of HDMI chip
HDMI_SPDIFOUT	in	14	NONE	3.3V	Audio output of HDMI chip
JTAGEN	--	82	--	--	Enable JTAG access to carrier CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) Set DIP switch S3-C JTAGEN to ON for accessing to the FPGA of the module Set DIP switch S3-C JTAGEN to OFF for accessing to CPLD of the carrier board (TE0701)
MIO10	inout	29	UP	3.3V	MIO pin
MIO11	inout	19	UP	3.3V	MIO pin
MIO12	inout	36	NONE	3.3V	MIO pin
MIO13	inout	30	NONE	3.3V	MIO pin
MIO14	inout	37	UP	3.3V	MIO pin / Module UART0.RX << BDBUS0 only for Microchip modules same as TEM0007.
MIO15	in	18	NONE	3.3V	MIO pin / Module UART0.TX >> BDBUS1 only for Microchip modules same as TEM0007.
MODE	out	27	DOWN	3.3V	Used as boot mode pin selector.
NOSEQ	inout	21	UP	3.3V	No Sequence, connected to the CPLD of module. This pin can be controlled via CM1 (S3-A) dip switch by user.
PG_C2M	out	20	NONE	3.3V	Power Good for FMC
PGOOD	inout	25	UP	3.3V	Connected to Module CPLD and used as boot mode pin selector. This pin can be controlled via CM2 (S4-D) dip switch by user.
PHY_LED1	out	42	NONE	3.3V	Displays the status of SD_DETECT signal.
PHY_LED2	out	43	NONE	3.3V	Displays the state of the selected generic parameters
POK_FMC	in	32	UP	3.3V	FMC Power good from FMC VADJ DCDC
PX6	inout	49	UP	3.3V	PMOD J2
PX7	inout	48	UP	3.3V	PMOD J2
RESIN	out	13	UP	3.3V	Connected to the module reset
~~REVISION_DETECION~~	in	57	--	--	~~REV06+ only: Detection / currently_not_used~~
S1	in	3	UP	3.3V	User Pushbutton / This pushbutton switchs between UART0 and UART1 only for Microchip modules same as TEM0007. / By pressing this button , the GPIO_output[7:0] will be displayed in LED1..8 only for AMD modules.
S2	in	2	UP	3.3V	Global Reset
SD_DETECT	in	40	UP	3.3V	SD card detection. This switch is connected to MODE pin in the firmware.
SD_WP	in	41	UP	3.3V	SD write protection pin
SEL_SD	out	39	DOWN	3.3V	SD Selection, MMC SD Slot or PMOD J2. It is set to '0' in the firmware permanently.
ULED1	out	78	NONE	3.3V	Displays the UART1 RXD signal
ULED2	out	77	NONE	3.3V	Displays the UART1 TXD signal
ULED3	out	76	NONE	3.3V	Displays the PGOOD signal status
ULED4	out	16	NONE	3.3V	Displays the NOSEQ signal status
ULED5	out	69	NONE	3.3V	Displays the boot mode state, if ON → JTAG boot mode
ULED6	out	68	NONE	3.3V	Displays the boot mode state, if ON → eMMC boot mode
ULED7	out	65	NONE	3.3V	Displays the boot mode state, if ON → SD card boot mode
ULED8	out	64	NONE	3.3V	Displays the boot mode state, if ON → QSPI boot mode
USB_OC	in	17	UP	3.3V	USB Over Current
VID0	out	34	UP	3.3V	VADJ Voltage selection (EN5335QI)/ Connected to high impedance in the firmware permanently
VID1	out	35	UP	3.3V	VADJ Voltage selection (EN5335QI)/ Connected to high impedance in the firmware permanently
VID2	out	38	UP	3.3V	VADJ Voltage selection (EN5335QI)/ Connected to high impedance in the firmware permanently
X6	in	60	NONE	3.3V	Module IO (powered by VIOTB (FMC VADJ))
Y0	in	75	UP	3.3V	I2C SCL (powered by VIOTB (FMC VADJ))
Y1	out	66	UP	3.3V	I2C SDA_OUT (powered by VIOTB (FMC VADJ))
Y2	in	67	UP	3.3V	RGPIO CLK (powered by VIOTB (FMC VADJ))
Y3	out	70	UP	3.3V	RGPIO TX (powered by VIOTB (FMC VADJ))
Y4	in	74	UP	3.3V	RGPIO RX (powered by VIOTB (FMC VADJ))
Y5	in	71	UP	3.3V	I2C SDA_IN (powered by VIOTB (FMC VADJ))
Y6	in	63	NONE	3.3V	Module IO (powered by VIOTB (FMC VADJ))

Functional Description

Dip Switch

DIP Switch S3
S3-A	S3-B	S3-C	S3-D	Description
CM1	CM0	JTAGEN	MIO0	JTAGEN set carrier board CPLD into the chain for firmware update. CM1 controls the NOSEQ signal. CM0 controls JTAGMODE signal to program the firmware of the CPLD chip.^* MIO0 is not connected to the CPLD of the carrier board.

^*Note that JTAGMODE signal does not work for the PCB REV06 or older. But it will work for PCB REV07 or newer, which is not produced yet.

DIP Switch S4
S4-A	S4-B	S4-C	S4-D	Description
VID0	VID1	VID2	CM2	VID0,1 and VID2 adjust the variable output voltage of EN5335QI regulator. (FMC_VADJ) CM2 dip switch controls the PGOOD signal.

JTAG

JTAGEN set CPLD of the carrier board TE0701 into the chain for firmware update. In normal mode JTAG is routed directly to the SoC module. Set S3-ENJTAG (S3-C) dip switch to OFF to get access to CPLD of the carrier board.

FMC JTAG is currently not enabled.

Power

EN1 is set to logical one .

~~EN_FMC is set to logical one or is controlled by I2C on I2C Mode.~~

~~PG_C2M is set to logical one or is controlled by I2C on I2C Mode.~~

VADJ

VADJ on PCB REV06+ S4 Control

~~This mode is only available on PCB Revision 06 or higher.~~

~~S4 control will be enabled on power on sequence or reset (S2-Button), if one of the three S4-DIP switches is set to one.~~

~~In this Mode I2C-controll is not selectable and S3-M1 and S3-M2 are available as User-DIP-Switch.~~

In the new firmware (CPLD firmware Version 07) the VADJ can not be adjustable via I2C more. This voltage can be selected only via S4 dip switch as shown:

S4-C (VID2)	S4-B (VID1)	S4-A (VID0)	Description
ON	ON	ON	VADJ: 3.3V
ON	ON	OFF	VADJ: 2.5V
ON	OFF	ON	VADJ: 1.8V
ON	OFF	OFF	VADJ: 1.5V
OFF	ON	ON	VADJ: 1.25V
OFF	ON	OFF	VADJ: 1.2V
OFF	OFF	ON	VADJ: 0.8V (Do not use, not supported as IO standard)
OFF	OFF	OFF	used to set VADJ control to REV05- or I2C control after power up sequence

VADJ on PCB REV05- S3 Control

~~S4 control will be disabled on power on sequence or reset (S2-Button), if all of the three S4-DIP switches is set to OFF or older PCB revision is used.~~

Note
~~Do not set S4-Switches to ON, if REV05- or I2C control is enabled.~~

~~S3-M1~~	~~S3-M2~~	~~Description~~
~~OFF~~	~~OFF~~	~~VADJ: 1.8V~~
~~OFF~~	ON	~~VADJ: 2.5V~~
ON	~~OFF~~	~~VADJ: 3.3V~~
On	ON	~~I2C controlled~~

VADJ on I2C Control

Disable S4 Control (see VADJ on PCB REV05- S3 Control) and set S3-M1 and S3-M2 to on. I2C VADJ Control use TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA) connected to module FPGA PL side. I2C-GPIO controller device address is 0x22. Transmitted data will be converted to a 8-bit GPIO bus.

Bit	Access	Default	Description
7	~~R/W~~	0	~~FMC - Enable~~
6	~~R/W~~	0	~~VID2~~
5	~~R/W~~	0	~~VID1~~
4	~~R/W~~	0	~~VID0~~
3	~~R/W~~	0	~~PG_C2M - Enable~~
2	R	x	~~POK_FMC (EN5335QI Power OK)~~
1	R	x	~~one: I2C Mode, zero: DIP Mode,~~
0	R	x	~~VID Mode (zero: S4-DIP-controlled, one: REV05-/I2C controlled)~~

~~VID2~~	~~VID1~~	~~VID0~~	~~Description~~
0	0	0	~~VADJ: 3.3V~~
0	0	1	~~VADJ: 2.5V~~
0	1	0	~~VADJ: 1.8V~~
0	1	1	~~VADJ: 1.5V~~
1	0	0	~~VADJ: 1.25V~~
1	0	1	~~VADJ: 1.2V~~
1	1	0	~~VADJ: 0.8V~~
1	1	1	~~reserved~~

~~To read I2C with petalinux use i2cget -y 0 0x22.~~

~~-y: do not confirm input~~
~~0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)~~
~~0x22 I2C GPIO controller on TE0701 CPLD~~

~~To write I2C with petalinux use i2cset -y 0 0x22 0x80~~

~~-y: do not confirm input~~
~~0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)~~
~~0x22 I2C GPIO controller on TE0701 CPLD~~
~~0x80: Enable FMC Power with VAD 3.3V, see I2C control table.~~

Reset

RESIN (negative Reset) to module, can be set by S2 button.

Boot Mode

Boot mode is set to SD-Boot, when SD-Card is detected.

FMC I2C

"3 wire split i2c" to to normal I2C:

Code Block

language	ruby

FMC_SDA       <= '0' when Y5='0' else 'Z';
FMC_SCL       <= Y0 and PON;
Y1            <= FMC_SDA;

I2C Interface

To read I2C with petalinux use i2cget -y 0 0x22.

-y: do not confirm input
0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
0x22 I2C GPIO controller on TE0701 CPLD

To write I2C with petalinux use i2cset -y 0 0x22 0x80

-y: do not confirm input
0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
0x22 I2C GPIO controller on TE0701 CPLD
0x80: Enable FMC Power with VAD 3.3V, see I2C control table.

RGPIO

~~RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.~~

~~RGPIO Pin to FPGA~~	~~Value~~
0	~~MIO10~~
1	~~MIO11~~
2	~~MIO12~~
3	~~MIO13~~
4	~~MIO14~~
5	~~MIO15~~
6	~~PX6~~
7	~~PX7~~
8	S1
9	~~CM0~~
10	~~CM1~~
11	~~CM2~~
12	~~SD_WP~~
13	~~SD_DETECT~~
14	~~USB_OC~~
15	~~POK_FMC~~
16	~~FMC_PRSNT~~
17	~~PGOOD~~
18	~~NOSEQ~~
19	~~unused~~
20	X6
21	Y6
~~22-23~~	~~unused~~
~~24-27~~	~~reserved~~
~~28-31~~	~~Interface detection~~

~~RGPIO Pin from FPAG~~	~~Value~~
~~0-7~~	~~LED 1-8~~
~~8-9~~	~~PHY_LED 1/2~~
~~10-23~~	~~unused~~
~~24-27~~	~~reserved~~
~~28-31~~	~~Interface detection~~

LED

LED	Description
ULED1	VADJ selection when RGPIO Bus is not active else RGPIO Bus Pin 0 VADJ selection: blink when VCCIO(VIOTB/VADJ) is disabled else on when VADJ on PCB REV05- or I2C Control or off when VADJ on PCB REV06+ S4 Control
ULED2	I2C control mode when RGPIO Bus is not active else RGPIO Bus Pin 1
ULED3	UART to Module activity when RGPIO Bus is not active else RGPIO Bus Pin 2
ULED4	UART to FTDI activity when RGPIO Bus is not active else RGPIO Bus Pin 3
ULED5	BOOTMODE (on Flash, off SD) when RGPIO Bus is not active else RGPIO Bus Pin 4
ULED6	CM2 when RGPIO Bus is not active else RGPIO Bus Pin 5
ULED7	X6 when RGPIO Bus is not active else RGPIO Bus Pin 6
ULED8	Y6 when RGPIO Bus is not active else RGPIO Bus Pin 7

PHY LED	Description
PHY_LED1	Y2 when RGPIO Bus is not active else RGPIO Bus Pin 8
PHY_LED2	Y4 when RGPIO Bus is not active else RGPIO Bus Pin 9

UART

It is two UART interfaces for Microchip modules and only one UART interface for AMD modules. For Microchip modules the UART interface be multiplexed between UART0 (HSS console) and UART1 (Linux console) via S1 user pushbutton. By booting in the beginning UART0 is connected to the UART interface ny default. The user can swith to UART1 (Linux console) by pressing the S1 pushbutton any time and vice versa. For microchip modules the *.jed file is special and the CPLD chip of the carrier board must be reprogrammed for this purpose.

UARTx	To	From	Signal	Description
UART0	MIO13	BDBUS0	Module UART0 RXD	Only for Microchip modules. The UART interface can be switched between UART0 (HSS console) and UART1(Linux console) via S1 pushbutton.
UART0	BDBUS1	MIO12	Module UART0 TXD	Only for Microchip modules. The UART interface can be switched between UART0 (HSS console) and UART1(Linux console) via S1 pushbutton.
UART1	MIO14	BDBUS0	Module UART1 RXD	For all AMD and Microchip modules
UART1	BDBUS1	MIO15	Module UART1 TXD	For all AMD and Microchip modules

Appx. A: Change History

Revision Changes

Changes REV06 to REV07:
- UART interface UART0 only for Microchip modules added
- S1 is used for multiplexing UART0 and UART1 for Microchip modules.
- LEDs and PHY_LEDs function is changed.
- I2C interface with 0x30 address is added. It is connected to MIO10 (SCL) and MIO11 (SDA).
- I2C interface with 0x22 address for HDMI chip is changed. It is connected to HDMI_SCL and HDMI_SDA.
- CPLD_REVISION as generic parameter is added.
- PGOOD is used as boot mode selector pin in addition to MODE pin (SD_DETECT). In addition to SD card /QSPI boot modes JTAG and eMMC boot modes can be selected.
- PGOOD, NOSEQ can be set or reset via CM2 (S4-D) and CM1 (S3-A) respectively.
- FMC_VADJ voltage can not be changed via firmware more. This variable votlage can be changed only via S4-A,B,C only.
- The CPLD of module can be programmed for REV07 or newer versions. JTAGMODE pin is added. JTAGMODE signal can be controlled with CM0 (S3-B) for PCB REV07 or newer versions.
- RGPIO is not used more.
Changes REV05 to REV6:
- Connecting PGOOD to CM2 to use as boot mode pin selector
- JTAG timing correction
Changes Older Revisions to REV05:

...

UART

...

Appx. A: Change History

Revision Changes

...

- Power Management
  - three VADJ Control Modi (REV06+ S4 Control, REV05- S3 Control and I2C Control)
- Reset Management
  - only little changes
- RGPIO Interface to FPGA
  - RGPIO support
- LED
  - new Order and accessible by RGPIO

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

Date

Document Revision

CPLD Firmware Revision

Supported PCB Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

...

REV05,REV6

John Hartfiel

Revision 05 finished

2016-04-11

v.1

---

Page info

	created-user
	created-user

Initial release

All

Page info

	modified-users
	modified-users

Appx. B: Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Appx. B: Legal Notices

...

chip unused pin
ADBUS4	out	98

v.29	REV05	REV03,REV04,REV05,REV6	John Hartfiel	Add FMC I2C description
2017-08-14	v.27	REV05	REV03,REV04,REV05,REV6	John Hartfiel	Description correction on port table
2017-06-08	v.26

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 29

New Version 30

Key

Table of contents

Overview

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

JTAG

Power

VADJ

VADJ on PCB REV06+ S4 Control

VADJ on PCB REV05- S3 Control

VADJ on I2C Control

Reset

Boot Mode

FMC I2C

RGPIO

LED

Functional Description

Dip Switch

JTAG

Power

VADJ

VADJ on PCB REV06+ S4 Control

VADJ on PCB REV05- S3 Control

VADJ on I2C Control

Reset

Boot Mode

FMC I2C

I2C Interface

RGPIO

LED

UART

Appx. A: Change History

Revision Changes

UART

Appx. A: Change History

Revision Changes

Document Change History

Appx. B: Legal Notices

Table of contents

Appx. B: Legal Notices