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- To start SDK project, run "TE::sw_run_sdk" on Vivado TCL-Console
Include Hardware-Definition-File, Bit-file and local Software-libraries from <design_name>/sw_lib/sw_apps - To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type "TE::sw_run_sdk -prebuilt_hdf <board_number>" on Vivado-TCL-Console
- To open an existing SDK-project without update HDF-Data, type "TE::sw_run_sdk -open_only" on Vivado-TCL-Console
Advanced Usage
Attention not all features of the TE-Scripts are supported in the advanced usage!
User defined board part csv file
| Name | Description | Value | |
|---|---|---|---|
| ID | ID to identify the board variant of the module series, used in TE-Scripts | Number, should be unique in csv list | |
| PRODID | Product ID, currently not used in TE-Scripts | Product Name | |
| PARTNAME | FPGA Part Name, used in Vivado and TE-Scripts | Part Name, which is available in Vivado, ex. xc7z045ffg900-2 | |
| BOARDNAME | Board Part Name, used in Vivado and TE-Scripts | Board Part Name or "NA", which is available in Vivado, NA is not defined to run without boardpart, ex. trenz.biz:te0782-02-45:part0:1.0 | |
| SHORTNAME | Subdirectory name, used for multi board projects to get correct sources and save prebuilt data | Name, should be unique in csv list | |
| ZYNQFLASHTYP | Flash typ used for programming Zynq-Devices via SDK-Programming Tools (program_flash) | "qspi_single" or "NA", NA is not defined | |
| FPGAFLASHTYP | Flash typ used for programming Devices via Vivado/LabTools | "<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32 Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build. |
To modifiy current csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.
User defined Settings
Vivado settings:
Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name>/settings/project_settings.tcl". This file will be loaded automatically on project creation.
Script settings:
Additional script settings (only some predefined variables) can be saved as a user defined file "<design_name>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.
ZIP ignore list:
Files which should not be added in the backup file can be can be defined in this file: "<design_name>/settings/zip_ignore_list.tcl". This file will be loaded automaticaly on script initialisation.
SDSOC settings:
SDSOC settings will be disposited on the following files: "<design_name>/settings/<design_name>_pfm.tcl" and "<design_name>/settings/<design_name>_sw.pfm"
HDL-Design
HDL files cane be saved in the subfolder "<design_name>/hdl/" or "<design_name>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv. A own top-file must be specified with the name "<design_name>_top.v" or "<design_name>_top.vhd".
To use source file in simulation only name must include "_simonly_", for synthese only "_synonly_".
RTL-IP-cores (*xci). can be saved in the subfolder "<design_name>/hdl/xci" or "<design_name>/hdl/xci/<shortname>". They will be loaded automatically on project creation.
Checklist / Troubleshoot
- Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
- Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
- Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
- Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
- If nothing helps, send a mail to trenz support (support(at)trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)
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