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Currently not supported functions:

• HSI dependet functions with UltraScale+ Series

Directory structure

Command Files

Command files will be generated with "_create_win_setup.cmd" on Windows  and "_create_linux_setup.sh" on Linux OS. Linux shell files are currently not available for this release.

Windows Command Files

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• Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
  (optional) Install Xilinx Vivado LabTools (Lab Edition)
• Configure the reference-design:
  1. Open “design_basic_settings.cmd” with a text-editor:
      a. Set correct Xilinx Environment:
          @set XILDIR=C:/Xilinx
          @set VIVADO_VERSION=2016.24
          Program settings will be search in :
          %XILDIR%/VIVADO/%VIVADO_VERSION%/
          %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
          %XILDIR%/SDK/%VIVADO_VERSION%/
          Example directory: c:/Xilinx/Vivado/2016.2/
          Attention: Scripts are supported only with predefined Vivado Version!
      b. Set the correct module part-number:
          @set PARTNUMBER=x
          You found the available Module Numbers in <design_name>/board_files/<board_series>_board_files.csv
      c. Set Application name (for programming with batch-files only):
          @set SWAPP=NA
          NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
         <app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
• Create all prebuilt files in one step:
  2. Run “design_run_project_batchmode.cmd”
• (optional to Step 2) Create all prebuilt files in single steps:
  3. Run “vivado_create_project_guimode.cmd”:
      A Vivado Project will be create and open  in ./vivado
  4. Type “TE::hw_build_design” on Vivado TCL-Console:
      Run Synthese, Implement and create Bitfile and optional MCSfile
  5. Type “TE::sw_run_hsi” on Vivado TCL-Console:
      Create all Software Applications from <design_name>/sw_lib/apps_list.csv
  6. (optional to Step 5) Type “TE::sw_run_sdk” on Vivado TCL-Console:
      Create a SDK Project in <design_name>/workspace/sdk
      Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps

• Programming FPGA or Flash Memory with prebuilt Files:
  7. Connect your Hardware-Modul with PC via JTAG.
  With Batch-file:
  8. (optional) Zynq-Devices Flash Programming (*.bin):
      Run “program_flash_binfile.cmd”
  9. (optional) FPGA-Device Flash Programming (*.mcs):
      Run “program_flash_mcsfile.cmd”
  10. (optional) FPGA-Device Programming (*.bit):
        Run “program_fpga_bitfile.cmd”
  With Vivado/Labtools TCL-Console:
  11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado  or LabTools
  12. (optional) Zynq-Devices Flash Programming (*.bin):
        Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
        Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  13. (optional) FPGA-Device Flash Programming (*.mcs):
        Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
        Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  14. (optional) FPGA-Device Programming (*.bit):
        Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
        Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

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SDSOC settings will are deposited on the following folder: "<design_name>/settings/sdsoc"

User defined TCL Script

TCL Files from "<design_name>/settings/usr" will be load automaticaly on script initialisation.

SDSOC-Template

SDSOC description and files to generate SDSoC project are deposited on the following folder: "<design_name>/settings/sdsoc"

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