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    • Important Note: QSPI Programming need special FSBL on 2017.4 or higher for all Zynq/ZynqMP. Special programming FSBL will be provided on all newer reference designs
    • Linux OS only: HSI VITIS software generation failed.
      • Reason: start "gmake" failed, alias is not set on Ubuntu
      • Workaround: "sudo ln -s /usr/bin/make /usr/bin/gmake" to generate alias or use  SDK GUI to generate applications and boot files.
    • Linux OS only: Function, which used external programs.
      • Reason: Currently only set correctly for Win OS.
      • Workaround: Change TCL scripts program path manually.

...

File or DirectoryTypeDescription
<design_name>base directoryBase directory with predefined batch files (*.cmd) to generate or open VIVADO-Project
<design_name>/block_design/sourceScript to generate Block Design in Vivado (*_bd.tcl). (optional) Some board part designs used subfolder <board_file_shortname>  with Board Part specific Block Design (*_bd.tcl).
<design_name>/board_files/sourceLocal board part files repository and a list of available board part files  (<board_series>_board_files.csv)
<design_name>/board_files/carrier_extensionsource(Optional) Additional TCL-Scripts to extend Board Part PS-Preset with carrier board specific settings.
<design_name>/consolesourcefolder with different console command files. Use _create_win_setup.cmd or _create_linux_setup.sh to generate files on top folder.
<design_name>/constraints/sourceProject constrains (*.xdc). Some board part designs used subfolder <board_file_shortname>  with additional constrains (*.xdc)
<design_name>/doc/sourceDocumentation
<design_name>/hdl/sourceHDL-File and XCI-Files. Advanced usage only!
<design_name>/firmware/sourceELF-File Location for MicroBlaze Firmware.  Additional sub folder is used for MicroBlaze identification.
<design_name>/ip_lib/sourceLocal Vivado IP repository
<design_name>/misc/source(Optional) Directory with additional sources
<design_name>/prebuilt/prebuiltContains a readme with location information of different assembly variants
<design_name>/prebuilt/boot_images/prebuiltDirectory with prebuilt boot images (*.bin) and configuration files (*.bif)  for zynq and configured hardware files (*.bit and *.mcs) for micoblaze included in sub-folders: default or <board_file_shortname>/<app_name>
<design_name>/prebuilt/hardware/prebuiltDirectory with prebuilt hardware sources (*.bit, *xsa, *.mcs) and reports included in subfolders: default or <board_file_shortname>
<design_name>/prebuilt/software/prebuilt(Optional) Directory with prebuilt software sources (*.elf) included in subfolders: default or <board_file_shortname>/<app_name>
<design_name>/prebuilt/os/prebuilt(Optional) Directory with predefined OS images included in subfolders  <os_name>/<board_file_shortname> or <os_name>/<ddr size>
<design_name>/scripts/sourceTCL scripts to build a project
<design_name>/settings/source(Optional) Additional design settings: zip_ignore_list.csv, vivado project settings, SDSOC settings
<design_name>/software/source(Optional) Directory with additional software
<design_name>/os/source(Optional) Directory with additional os sources in in subfolders  <os_name>
<design_name>/sw_lib/source(Optional) Directory with local SDK/HSI Vitis software IP repository and a list of available software (apps_list.csv)
<design_name>/v_log/generated(Temporary) Directory with vivado log files (used only when Vivado is started with predefined command files (*.cmd) from base folder otherwise this logs will be writen into the vivado working directory)
<design_name>/vivado/work, generated(Temporary) Working directory where Vivado project is created. Vivado project file is <design_name>.xpr
<design_name>/vivado_lab/work, generated(Optional/Temporary) Working directory where Vivado LabTools is created. LabTools project file is <design_name>.lpr
<design_name>/workspace/hsiobsolete(Optional/Temporary) Directory where hsi project is created
<design_name>/workspace/sdkwork, generated(Optional) Directory where Vitis project is created
<design_name>/tmp/work, generated(Optional) Directory  for some tasks
<design_name>/_binaries_<articlenumber>generatedexport directory for binaries (run _create_win_setup.cmd and follow instructions)
<design_name>/.../SDSoC_PFMobsolete(Optional) Directory where SDSOC project is created
<design_name>/backup/generated(Optional) Directory for project backups

...

File NameDescription
Design + Settings
_create_win_setup.cmd

Use to create bash files. With 2018.3 and newer also "Module Selection Guide" is included and with 2019.2 prebuilt export for the selected variant

_use_virtual_drive.cmd(Option) Create virtual drive for project execution. See Xilinx AR#52787
design_basic_settings.cmd

Settings for the other *.cmd files. Following Settings are avaliable:

  • General Settings:
    • (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing
    • (optional) ZIP_PATH: Set Path to installed Zip-Program. Currently 7-Zip are supported. IUsed for predefined TCL-function to Backup project.
    • (optional) ENABLE_SDSOC: Enable SDSOC Setting. Currently only for some reference project as beta version!
  • Xilinx Setting:
    • XILDIR: Set Xilinx installation path (Default: c:\Xilinx).
    • VIVADO_VERSION: Current Vivado/LabTool/SDK Version (Example:2019.2). Don't change Vivado Version.
      • Xilinx Software will be searched in:

      • VIVADO (optional for project creation and programming): %XILDIR%\Vivado\%VIVADO_VERSION%\

      • Vitis (optional for software projects and programming): %XILDIR%\Vitis\%VIVADO_VERSION%\

      • LabTools (optional for programming only): %XILDIR%\Vivado_Lab\%VIVADO_VERSION%\

  • Board Setting:
    • PARTNUMBER: Set Board part number of the project which should be created
      • Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list)
      • Used for project creation and programming
      • To create empty project without board part, used PARTNUMBER=-1 (use GUI to create your project. No block design tcl-file should be in /block_design)
      • Example TE0726 Module :
      • USE ID                 |USE PRODID                                   
        PARTNUMBER=1 |PARTNUMBER=te0726-01  
  • Programming Settings(program*file.cmd):
    • SWAPP: Select Software App, which should be configured.
      • Use the folder name of the <design_name>/prebuilt/boot_image/<partname>/* subfolder. The *bin,*.mcs or *.bit from this folder will be used.
      • If you will configure the raw *.bit or *.mcs  *.bin  from the <design_name>/prebuilt/hardware/<partname>/ folder, use @set SWAPP=NA or @set SWAPP="".
      • Example: SWAPP=hello_world   → used the file from prebuilt/boot_image/<partname>/hello_world
                        SWAPP=NA                → used the file from <design_name>/prebuilt/boot_image/<partname>/
    • PROGRAM_ROOT_FOLDER_FILE: If you want to program design file from the rootfolder <design_name>, set to 1

      • Attention: it should be only one *.bit, *.msc or *.bin file in the root folder.

design_clear_design_folders.cmd(optional)  Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files
design_run_project_batchmode.cmd

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/hsisdk/" directory with related documents before Project will created.

Hardware Design

vivado_create_project_guimode.cmd

Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process.

Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_create_project_batchmode.cmd

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_open_existing_project_guimode.cmdOpens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables.
Software Design
sdk_create_prebuilt_project_guimode.cmd(optional) Create Vitis project with hardware definition file from prebuild folder. It used the *.xsafrom: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd".
Programming
program_flash.cmd(optional)  Programming Flash Memory via JTAG with specified *.bin (Zynq devices) or *.mcs (native FPGA). Used  LabTools Programmer (Vivado or LabTools only. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd".
program_flash_binfile.cmdobsolete (optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK  "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd".
program_flash_mcsfile.cmdobsolete (optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
program_fpga_bitfile.cmd(optional)  Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd".
labtools_open_project_guimode.cmd

(optional)  Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".

...

File NameStatusDescription
Design + Settings
_create_linux_setup.shavailableUse to create bash files. With 2018.3 and newer also "Module Selection Guide" is included and with 2019.2 prebuilt export for the selected variant
design_basic_settings.shavailable

Settings for the other *.cmd files. Following Settings are avaliable:

  • General Settings:
    • (optional) DO_NOT_CLOSE_SHELL: Shell do not closed after processing
    • (optional) ZIP_PATH: Set Path to installed Zip-Program. Currently 7-Zip are supported. IUsed for predefined TCL-function to Backup project.
    • (optional) ENABLE_SDSOC: Enable SDSOC Setting. Currently only for some reference project as beta version!
  • Xilinx Setting:
    • XILDIR: Set Xilinx installation path (Default: /opt/Xilinx/).
    • VIVADO_VERSION: Current Vivado/LabTool/SDK Version (Example:2019.2). Don't change Vivado Version.
      • Xilinx Software will be searched in:

      • VIVADO (optional for project creation and programming): %XILDIR%/Vivado/%VIVADO_VERSION%/ and for SDSoC on %XILDIR%\SDx\%VIVADO_VERSION%\Vivado\

      • Vitis (optional for software projects and programming): %XILDIR%/SDK\%VIVADO_VERSION%/

      • LabTools (optional for programming only): %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/

  • Board Setting:
    • PARTNUMBER: Set Board part number of the project which should be created
      • Available Numbers: (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list)
      • Used for project creation and programming
      • To create empty project without board part, used PARTNUMBER=-1 (use GUI to create your project. No block design tcl-file should be in /block_design)
      • Example TE0726 Module :
      • USE ID                 |USE PRODID                                    
        PARTNUMBER=1 |PARTNUMBER=te0726-01
  • Programming Settings(program*file.cmd):
    • SWAPP: Select Software App, which should be configured.
      • Use the folder name of the <design_name>/prebuilt/boot_image/<partname>/* subfolder. The *bin,*.mcs or *.bit from this folder will be used.
      • If you will configure the raw *.bit or *.mcs  *.bin  from the <design_name>/prebuilt/hardware/<partname>/ folder, use @set SWAPP=NA or @set SWAPP="".
      • Example: SWAPP=hello_world   → used the file from prebuilt/boot_image/<partname>/hello_world
                        SWAPP=NA                → used the file from <design_name>/prebuilt/boot_image/<partname>/
    • PROGRAM_ROOT_FOLDER_FILE: If you want to program design file from the rootfolder <design_name>, set to 1

      • Attention: it should be only one *.bit, *.msc or *.bin file in the root folder.

design_clear_design_folders.shnot available(optional)  Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files
design_run_project_bashmode.shnot available

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/hsisdk/" directory with related documents before Project will created.

Hardware Design

vivado_create_project_guimode.shavailable

Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process.

Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_create_project_bashmode.shnot available

(optional)  Create Project with setting from "design_basic_settings.cmd" and source folders.

Delete  "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created.

If old vivado project exists, type "y" into the command line input to start project creation again.

vivado_open_existing_project_guimode.shavailableOpens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables.
Software Design
sdk_create_prebuilt_project_guimode.shnot available(optional) Create SDK project with hardware definition file from prebuild folder. It used the *.hdfxsa from: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd".
Programming
program_flash.shnot available(optional)  Programming Flash Memory via JTAG with specified *.bin (Zynq devices) or *.mcs (native FPGA). Used  LabTools Programmer (Vivado or LabTools only. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.sh".
labtools_open_project_guimode.shnot available

(optional)  Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd".

...

  • Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
    (optional) Install Xilinx Vivado LabTools (Lab Edition)
  • Automatically configuration of the reference-designs (only with 2018.3 scripts and newer):
    • Run "_create_win_setup.cmd" or "_create_linux_setup.sh"
      • select "module selection guide" and follow instructions.
        • "design_basic_settings.cmd" will be configured over this menu
  • (optional for 18.3 or newer) Manual Configure the reference-design (Note: batch/bash files works only in the basefolder of the project, use _create_*_setup.cmd/sh or copy manually ):
    1. Open “design_basic_settings.cmd” with a text-editor:
        a. Set correct Xilinx Environment:
            @set XILDIR=C:/Xilinx
            @set VIVADO_VERSION=2019.2
            Program settings will be search in :
            %XILDIR%/VIVADO/%VIVADO_VERSION%/
            %XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
            %XILDIR%/Vitis/%VIVADO_VERSION%/
            Example directory: c:/Xilinx/Vivado/2019.2/
            Attention: Scripts are supported only with predefined Vivado Version!
        b. Set the correct module part-number:
            @set PARTNUMBER=x
            You found the available Module Numbers in <design_name>/board_files/<board_series>_board_files.csv
        c. Set Application name (for programming with batch-files only):
            @set SWAPP=NA
            NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
           <app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
  • Create all prebuilt files in one step:
    2. Run “design_run_project_batchmode.cmd”
  • (optional to Step 2) Create all prebuilt files in single steps:
    3. Run “vivado_create_project_guimode.cmd”:
        A Vivado Project will be create and open  in ./vivado
    4. Type “TE::hw_build_design” on Vivado TCL-Console:
        Run Synthese, Implement and create Bitfile and optional MCSfile
    5. Type “TE::sw_run_hsivitis -all -no_gui” on Vivado TCL-Console:
        Create all Software Applications from <design_name>/sw_lib/apps_list.csv
    6. (optional to Step 5) Type “TE::sw_run_sdkvitis ” on Vivado TCL-Console:
        Create a SDK Project in <design_name>/workspace/sdk
        Include Hardware-Definition-File, Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps

  • Programming FPGA or Flash Memory with prebuilt Files:
    7. Connect your Hardware-Modul with PC via JTAG.
    With Batch-file:
    8. (optional) Zynq-Devices Flash Programming (*.bin) :
        Run “program_flash_binfile.cmd”
    9. (optional) or FPGA-Device Flash Programming (*.mcs):
        Run “program_flash_mcsfile.cmd”
    10. (optional) FPGA-Device Programming (*.bit):
          Run “program_fpga_bitfile.cmd”
    With Vivado/Labtools TCL-Console:
    11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado  or LabTools
    12. (optional) Zynq-Devices Flash Programming (*.bin):
          Type “TE::pr_program_flash _binfile -swap <app_name>” on Vivado TCL-Console
          Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
    13. (optional) FPGA-Device Flash Programming (*.mcs):
          Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
          Used *.mcs from Used .bin(Zynq)/.mcs(native FPGA) <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
    1413. (optional) FPGA-Device Programming (*.bit):
          Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
          Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>

...

  • Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance>.
  • For MCS-Core use MCS IP Instance Name. This name must use *mcs* or *syscontrol* in the name.


Software Design

...

Vitis: Generate predefined software from libraries

  • To generate predefined software from libraries, run "TE::sw_run_hsi_vitis -all -no_gui" on Vivado TCL-Console
  • All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticity
  • Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app

...


VITIS: Create user software project

  • To start SDK project, run "TE::sw_run_sdkvitis" on Vivado TCL-Console or run "TE::sw_run_vitis -workspace_only" on Vivado TCL-Console
    Include Hardware-Definition-File (XSA), Bit-file and local Software-libraries from  <design_name>/sw_lib/sw_apps
  • To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type  "TE::sw_run_sdk vitis -prebuilt_hdf xsa <board_number>" on Vivado-TCL-Console
  • To open an existing SDK-project without update HDF-Data, type  "TE::sw_run_sdk vitis -opengui_only" on Vivado-TCL-Console

...