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JTAGEN set carrier board CPLD into the chain for firmware update. In normal mode JTAG is routed directly to Module. Set S3-ENJTAG to OFF to get access to carrier CPLD.
FMC JTAG is currently not enabled.
EN1 is set to logical one .
EN_FMC is set to logical one or is controlled by I2C on I2C Mode.
PG_C2M is set to logical one or is controlled by I2C on I2C Mode.
This mode is only available on PCB Revision 06 or higher.
S4 control will be enabled on power on or Reset (S2-Button), if one of the three S4-DIP switches is set to one.
In this Mode I2C-controll is not selectable and S3-M1 and S3-M2 are available as User-DIP-Switch.
S4-3(VID2) | S4-2(VID1) | S4-1(VID0) | Description |
---|---|---|---|
ON | ON | ON | VADJ: 3.3V |
ON | ON | OFF | VADJ: 2.5V |
ON | OFF | ON | VADJ: 1.8V |
ON | OFF | OFF | VADJ: 1.5V |
OFF | ON | ON | VADJ: 1.25V |
OFF | ON | OFF | VADJ: 1.2V |
OFF | OFF | ON | VADJ: 0.8V |
OFF | OFF | OFF | Used to set VADJ Control to REV05- control after power up sequence |
S4 control will be disabled on power on or Reset (S2-Button), if all of the three S4-DIP switches is set to OFF or older PCB revison is used.
S3-M1 | S3-M2 | Description |
---|---|---|
OFF | OFF | VADJ: 1.8V |
OFF | ON | VADJ: 2.5V |
ON | OFF | VADJ: 3.3V |
On | ON | I2C controlled |
RESIN (negative Reset) to module, can be set by S2 button.
Boot mode is set to SD-Boot, when SD-Card is detected.
RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.
LED | Description |
---|---|
ULED1 | |
ULED2 | |
ULED3 | |
ULED4 | |
ULED5 | |
ULED6 | |
ULED7 | |
ULED8 |
To | From | Description |
---|---|---|
MIO14 | BDBUS0 | Module UART0.RX |
BDBUS1 | MIO15 | Module UART0.TX |
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