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Table of Contents |
Overview
The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...
Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.
TE0716 is a commercial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020, with 1GB of DDR3L-1600 SDRAM, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages.
Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.
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Notes : |
Key Features
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- Xilinx XC7Z020 SoC:
- Processing system (PS):
- ARM® CortexTM-A9 MPCoreTM with CoreSightTM.
- L1 Cache: 32KB Instruction, 32KB Data per processor.
- L2 Cache: 512KB.
- Programmable logic (PL):
- Artix-7 FPGA Equivalent.
- Logic cells: 85K.
- Look-Up Tables: 53200.
- Block RAM: 4.9 Mb.
- DSP slices: 220.
- Peak DSP performance: 276 GMACs.
- 2x 12 bit, 1 MSPS ADCs with up to 17 Differential Inputs.
- 120 x PL HR I/O (48 differential pairs and 24 single-ended).
- 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
- 1GByte DDR3L SDRAM memory (2 x [256Mbit x 16]), 32-bit wide data bus.
- 32MByte Quad SPI Flash memory.
- MAC address serial EEPROM with EUI-48TM node identity (24AA025E48).
- 512Kb Serial EEPROM memory (CAT24C512).
- 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
- Gigabit Ethernet transceiver PHY (Marvell 88E1512).
- Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK).
- Single chip USB Interface 2.0 High Speed 480Mbs to UART / JTAG(Xilinx License included) (FTDI FT2232H-56Q), including microUSB-B connector.
- 2xUser RGB LEDs (Green), LED FPGA DONE (Green).
- 2 x Tactile Switches (User), 1 x Tactile Switche (Reset).
- Card Connector microSD™.
- On-board high-efficiency DC-DC converters for all voltages used.
- Board Size: 65 x 45 mm
- <Replace for module use "SoC/FPGA" for Carrier "Modules">
- RAM/Storage
- On Board
- Interface
- Power
- Dimension
- Notes...
Block Diagram
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title | TExxxx block diagram |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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title | TExxxx main components |
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- ...
- ...
- ...
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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Storage device name | Content | Notes |
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Quad SPI Flash |
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| EEPROM |
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| System Controller CPLD |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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anchor | Table_OV_RST |
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title | Reset process. |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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title | General PL I/O to B2B connectors information |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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JTAG Signal | B2B Connector |
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TMS |
| TDI |
| TDO |
| TCK |
| JTAG_EN |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_SIP_MIOs |
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title | MIOs pins |
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MIO Pin | Connected to | B2B | Notes |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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Test Point | Signal | Connected to | Notes |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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anchor | Table_OBP |
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title | On board peripherals |
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Chip/Interface | Designator | Notes |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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MIO Pin | Schematic | U?? Pin | Notes |
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RTC
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anchor | Table_OBP_RTC |
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title | I2C interface MIOs and pins |
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orientation | portrait |
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MIO Pin | Schematic | U? Pin | Notes |
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anchor | Table_OBP_I2C_RTC |
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title | I2C Address for RTC |
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orientation | portrait |
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MIO Pin | I2C Address | Designator | Notes |
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EEPROM
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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MIO Pin | Schematic | U?? Pin | Notes |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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orientation | portrait |
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sortDirection | ASC |
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MIO Pin | I2C Address | Designator | Notes |
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LEDs
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Designator | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
...
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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orientation | portrait |
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U?? Pin | Signal Name | Connected to | Signal Description | Note |
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CAN Transceiver
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anchor | Table_OBP_CAN |
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title | CAN Tranciever interface MIOs |
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orientation | portrait |
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cellHighlighting | true |
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Bank | Schematic | U?? Pin | Notes |
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| D-Tx |
| Driver Input |
| R-Rx |
| Reciever Output |
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Clock Sources
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anchor | Table_OBP_CLK |
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title | Osillators |
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orientation | portrait |
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sortDirection | ASC |
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Designator | Description | Frequency | Note |
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| KHz |
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
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anchor | Table_OBP_PCLK |
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title | Programmable Clock Generator Inputs and Outputs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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U?? Pin
| Signal | Connected to | Direction | Note |
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IN0 |
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| IN1 |
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| IN2 |
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| IN3 |
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| XAXB |
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| SCLK |
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| SDA |
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| OUT0 |
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| OUT1 |
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| OUT2 |
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| OUT3 |
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| OUT4 |
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| OUT5 |
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| OUT6 |
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| OUT7 |
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| OUT8/OUT9 |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Power-On Sequence
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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Power Rails
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anchor | Table_PWR_PR |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Scroll Title |
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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| PD:6 x 6 SoM LSHM B2B Connectors |
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...
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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orientation | portrait |
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Symbols | Description | Min | Max | Unit |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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style | |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
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Scroll Title |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Scroll Ignore |
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scroll-pdf | true |
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scroll-office | true |
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scroll-epub | true |
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scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Currently Offered Variants
Page properties |
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
...
Scroll Title |
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
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Scroll Title |
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Document Change History
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_RH_DCH |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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...