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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | IC Designator | Content | Notes |
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Quad SPI Flash | U7 | Empty | - | | 512Kb Serial EEPROM | U21 | Empty | - | | 2Kb 24AA025E48 EEPROM | U24 | Pre-programmed globally unique, 48-bit node address (MAC). | - | | 4Kb M93C66-R EEPROM | U40 | Xilinx JTAG Programmer License- | For FTDI IC only (U39). |
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Configuration Signals
| Page properties |
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- Overview of Boot Mode, Reset, Enables.
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- Part number: S25FL256SAGBHI20*
- Supply voltage: 3.3V (2.7V - 3.6V).
- Speed: 133MHz max.*
- Temperature: Industrial Range -40°C to +85°C.
Notes: * standard number/value but depends on assembly version.
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U7 Pin | Notes |
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| MIO1 | SPI-CS | CS# | - | | MIO3 | SPI-DQ1/M1 | SO/IO1 | - | | MIO4 | SPI-DQ2/M2 | WP#/IO2 | - | | MIO2 | SPI-DQ3/M3 | HOLD#/IO3 | - | | MIO5 | SPI-DQO/M0 | SI/IO0 | - | | MIO6 | SPI-SCK/M4 | SCK | - |
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| I2C Device | I2C Address | Designator | Notes |
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| 2K Serial EEPROMs with EUI-48™ | 0xA6 (write)
0xA7 (read)
0x53 (7bit) | U24 | - | 512Kb Serial EEPROM0xA0 (write)
0xA1 (read) | 0x50 (7bit) | U21 | - |
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ADCs
The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.
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| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title | Board hardware revision number. |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| |
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| diagramName | RH-HRN-TE0716-01 |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | top |
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| lbox | true |
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| diagramWidth | 265545 |
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| revision | 34 |
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| Scroll Only |
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Document Change History
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