Page History

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ED: Tabelle sollte fertig sein!

Changes

#1 Changed DDR4 SDRAM (U2, U3, U9, U12) from K4A8G165WB-BIRC to K4A8G165WC-BITDTCV. Set resistor (R68) to not fitted.

Type: Schematic Change

Reason: BOM Optimization.

Impact: DDR timing needs to be considered in customer design. Trenz Reference Design reflects it without changing timing but custom firmware needs to be checked and eventually updated by customer.

#1 Changed DCDC EN63A0QI (U4) to MPQ8633BGLE-Z and adapted power circuit.

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Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#2 Changed DCDC TPS82085SIL/MUN3CAD03-SE (U13) to MPM3860GQW-Z and adapted power circuit. Added pull-up resistor (R77) for signal "PG_VCU". (ED: ???)

Type: Schematic Change

Reason: Increase current capability.

Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#1 Changed DCDC (U15, U19, U20, U21, U22, U23, U24, U29, U30, U31, U38) from TPS82085SIL/MUN3CAD03-SE to MPM3834CGPA and adapted according circuit. (R91 ED: ???)

Type: Schematic Change

Reason: BOM Optimization.

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Impact: None. More DDR4 Chips are usable.

#6 Enabled DDR4 test usage via connecting DDR4-TEN signals together for DDR4 memory (U2, U3, U9, U12) and pulling them down

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via 499 Ohm resistor (R103). Added testpoint (TP3) for signal DDR4-TEN.

Type: Schematic Change

Reason: Enable DDR4 test improvement.

Impact: None.

#9 Added option to use remote senses for

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DCDC (U29, U30, U31) via resistor

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Type: Schematic Change

Reason: Remote sense option.

Impact: None.

#9 Added option to use remote senses for DCDCs U30 via resistor R90 (Default: not fitted).

Type: Schematic Change

Reason: Remote sense option.

Impact: None.

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(R13, R90, R106) (Default: not fitted).

Type: Schematic Change

Reason: Remote sense option.

Impact: None.

#17 Added additional decoupling capacitors C136, C149...

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C152, C155, C156, C201...C212, C216...C234.

Type: Schematic Change

Reason: Improve decoupling.

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Reason: BOM Optimization.

Impact: None.

#18 Changed 100 nF capacitor (C37, C79, C95, C96, C130, C131, C133) from 6.3 V, X5R, 0201 to 50 V, X7R, 0402.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#20 Changed capacitor (C12 ... C16, C18 ... C21, C42, C44, C45, C170, C171) from 4.7 µF to .10 µF

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Type: Schematic Change

Reason: BOM Optimization.

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#19 Changed 10 µF capacitor (C65 ... C67) from 16 V, 0603 to 6.3 V, 0401.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#19 Changed capacitor (C129, C132, C140 ... C148, C153) from 10 µF, 16 V to 22 µF, 10 V.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None.

#18 Changed capacitor (C73, C75) from 100 µF, 6.3 V, 1206 to 22 µF, 10 V, 0603.

Type: Schematic Change

Reason: BOM Optimization.

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Impact: Changed trace length have to be taken into account in existing designs. The trace length for new revision will be available in TE080x series pinout generator. Please check if change in trace length still matches your requirements. Adaption of carrier may be necessary.

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#24 Added system and power diagram. Updated legal notices and revision history. Updated page count and order. 

Type: Documentation Update

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