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Old Version 6

changes.mady.by.user John Hartfiel

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New Version 7

changes.mady.by.user John Hartfiel

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Feature Summary

  • Power Management
  • Boot Mode
  • Reset
  • UART

  • IO Expender(RGPIO)

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Name / opt. VHD NameDirectionPinBank PowerDescription
BM2/MIO4   / BM2_MIO4outB353.3VBoot Mode Pin to FPGA (SD or QSPI)
BOOTMODE   outB323.3VB2B UART from MIO15
CONFIGX  inB333.3VB2B UART to MIO14
CPLD_GPIO0 
A33.3VB2B / currently_not_used
CPLD_GPIO1 
B13.3VB2B / currently_not_used
CPLD_GPIO2 
A13.3VB2B / currently_not_used
CPLD_GPIO3 inA23.3VB2B, used for Boot Mode
DONE inA353.3VFPGA Done signal
EN_1VoutB33.3Vdisable/enable module power 1V and all other related voltages
EXT_IO1inoutA33EXT_IO_VCCB2B, RGPIO /
EXT_IO10 inoutB22EXT_IO_VCCB2B, RGPIO
EXT_IO11 inoutA24EXT_IO_VCCB2B, RGPIO
EXT_IO12 inoutA23EXT_IO_VCCB2B, RGPIO
EXT_IO13 inoutB21EXT_IO_VCCB2B, RGPIO
EXT_IO14 inoutA28EXT_IO_VCCB2B, RGPIO
EXT_IO15 inoutB18EXT_IO_VCCB2B, RGPIO
EXT_IO16 inoutA22EXT_IO_VCCB2B, RGPIO
EXT_IO17 inoutB8EXT_IO_VCCB2B, RGPIO
EXT_IO18 inoutA9EXT_IO_VCCB2B, RGPIO
EXT_IO19 inoutA20EXT_IO_VCCB2B, RGPIO
EXT_IO2inoutB24EXT_IO_VCCB2B, RGPIO
EXT_IO20 inoutB14EXT_IO_VCCB2B, RGPIO
EXT_IO21 inoutA8EXT_IO_VCCB2B, RGPIO
EXT_IO22 inoutB7EXT_IO_VCCB2B, RGPIO
EXT_IO23 inoutB13EXT_IO_VCCB2B, RGPIO
EXT_IO24 inoutA18EXT_IO_VCCB2B, RGPIO
EXT_IO25 inoutA5EXT_IO_VCCB2B, RGPIO
EXT_IO26 inoutB4EXT_IO_VCCB2B, RGPIO
EXT_IO27 inoutA13EXT_IO_VCCB2B, RGPIO
EXT_IO28 inoutA17EXT_IO_VCCB2B, RGPIO
EXT_IO29 inoutA6EXT_IO_VCCB2B, RGPIO
EXT_IO3inoutA27EXT_IO_VCCB2B, RGPIO
EXT_IO30 inoutB5EXT_IO_VCCB2B, RGPIO
EXT_IO31 inoutB12EXT_IO_VCCB2B, RGPIO
EXT_IO32 inoutA16EXT_IO_VCCB2B, RGPIO
EXT_IO33 inoutA7EXT_IO_VCCB2B, RGPIO
EXT_IO34 inoutB9EXT_IO_VCCB2B, RGPIO
EXT_IO35 inoutA15EXT_IO_VCCB2B, RGPIO
EXT_IO36 inoutB15EXT_IO_VCCB2B, RGPIO
EXT_IO37 inoutA11EXT_IO_VCCB2B, RGPIO
EXT_IO38 inoutA12EXT_IO_VCCB2B, RGPIO
EXT_IO39 inoutB16EXT_IO_VCCB2B, RGPIO
EXT_IO4inoutB20EXT_IO_VCCB2B, RGPIO
EXT_IO40 inoutA21EXT_IO_VCCB2B, RGPIO
EXT_IO5inoutA31EXT_IO_VCCB2B, RGPIO
EXT_IO6inoutB23EXT_IO_VCCB2B, RGPIO
EXT_IO7inoutA26EXT_IO_VCCB2B, RGPIO
EXT_IO8inoutA25EXT_IO_VCCB2B, RGPIO
EXT_IO9inoutA30EXT_IO_VCCB2B, RGPIO
FPGA_CPLD1 inA403.3VFPGA AB18/ currently_not_used, RGPIO CLK
FPGA_CPLD2 outB283.3VFPGA AB20/ currently_not_used, RGPIO out
FPGA_CPLD3 inA383.3VFPGA AD20/ currently_not_used, RGPIO in
FPGA_CPLD4 inA363.3VFPGA AE20 goes to LED2/ currently_not_used
JTAGENBinB303.3VEnable CPLD JTAG access, otherwiste otherwise M_... is used as GPIO
LED2outB10EXT_IO_VCCStatus LED D1 red
M_TCKinA453.3VJTAG if JTAGENB is high/ currently_not_used
M_TDIinA473.3VJTAG if JTAGENB is high/ currently_not_used
M_TDOoutA483.3VJTAG if JTAGENB is high/ currently_not_used
M_TMSinB343.3VJTAG if JTAGENB is high/ currently_not_used
MIO14outA443.3VUART out to FPGA
MIO15inA423.3VUART in from FPGA 
nRST_INinA323.3VReset from B2B to PS_POR
PG_ALLinA463.3VStatus power
PROG_B inB253.3VStatus PROG_B/ currently_not_used
PS_POR inoutA413.3Vopen drain as second reset from nRSR_IN/ currently_not_used
NC
B293.3Vdummy pin / not connected
NC
B273.3Vnot connected
NC
A343.3Vnot connected


Functional Description

JTAG

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  • RGPIO CLK is  FPGA_CPLD1 (max 25MHzup to 50MHz).
  • Output is FPGA_CPLD2
  • Input is FPGA_CPLD3

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