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Design Name always "TE Series Name" + Design name, for example "TEI0006 Test Board"

DateVersionChangesAuthor
2022-06-152.2
  • add 'QSPI-Boot mode'
  • add 'Get prebuilt boot binaries'
  • changed SD-Boot mode chapter
  •  'Device Tree' chapter expanded
TD
2022-04-212.1
  • update to 21.x
TD
2022-02-282.0
  • add yocto to
    • Overview → Key Features
    • Overview → Requirements
    • Design Flow
    • Launch
  • add section 'Software Design - Yocto'
TD
2021-06-151.2
  • table of content view
  • template history
  • placed a horizontal separation line under each chapter heading
  • replaced <design name> by <project folder>
  • changed title-alignment for tables from left to center
  • update 19.x to 20.x
JH,TD
2020-11-241.1
  • add fix table of content
  • add table size as macro
JH
--1.0----


Custom_table_size_100

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Important General Note:

  • Export PDF to download, if quartus revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

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        ExampleComment
        12



  • ...

Overview

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Notes :

Refer to http://trenz.org/te0xyztei0050-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Quartus Prime Pro Lite 21.41.1
  • Yocto
  • NIOS II
  • UART
  • ETH
  • USB
  • I2C
  • QSPI flash
  • DDR3 SDRAM memory
  • User LED
  • User button

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


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DateQuartusProject BuiltAuthorsDescription
2022-
04
08-
21
1121.1.
4 Pro
1 Lite
TEI0006

TEI0050-test_board_noprebuilt-quartus_21.

4

1.

0

1-

20220421183824

20220811093744.zip

TEI0006

TEI0050-test_board-quartus_21.

4

1.

0

1-

20210421183915

20220811093807.zip

Thomas Dück
  • initial release


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
No known issues---------


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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SoftwareVersionNote
Quartus Prime ProLite21.41.1needed
NIOS II SBT for Eclipse---optional


Hardware

Yocto
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dunfelloptional (more information: Yocto KICKstart#Used source files)
SI ClockBuilder Pro---optional

Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Complete List is available on <project folder>/board_files/*_board_files.csv

Design supports following modules:

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Module ModelBoard Part Short
NameYocto Machine
NamePCB Revision SupportDDRQSPI Flash
EMMC
OthersNotes

*used as reference

Design supports following carriers:

TEI0050-01-AAH11AAH11REV018MByte2MByte----
TEI0050-01-AAH13A*AH13REV018MByte8MByte----

*used as reference

Design supports following carriers:

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Carrier ModelNotes
---

*used as reference

Additional HW Requirements:

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Additional HardwareNotes
USB cable for JTAG/UARTCheck Carrier Board and Programmer for correct type

*used as reference

Content

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Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - Intel devices

Design Sources

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TypeLocationNotes
Quartus

<project folder>/source_files/quartus

<project folder>/source_files/<Board Part Short Name>/quartus

Quartus project will be generated by TE Scripts

(Optional) Source files for specific assembly variants

Software

Software

<project <project folder>/source_files/software

<project folder>/source_files/<Board Part Short Name>/software

Additional software will be generated by TE Scripts(Optional) Source files for specific assembly variants

Yocto<project folder>/source_files/os/yoctoYocto BSP layer template for linux


Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
      SRAM Object File*.sofRam configuration file
      Programmer Object File*.pofFPGA configuration file
      JTAG Indirect Configuration file*.jicFlash configuration file
      Raw binary file*.rbfFPGA configuration file
      Diverse Reports---Report files in different formats
      Software-Application-File*.elfSoftware application for NIOS II processor system

      Device Tree

      *.dtbDevice tree blob
      SFP-File*.sfpBoot image with SPL (Secondary Program Loader)
      BIN-File*.binImage with linux kernel and ram disk
      CONF-File*.confBoot configuration file (extlinux.conf)
      Yocto linux image*.wicLinux image for SD card




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File

File-Extension

Description

SOPC Information File*.sopcinfoFile with description of the .qsys file to create software for the target hardware
SRAM Object File*.sofRam configuration file
JTAG indirect configuration file*.jicFlash configuration file
Raw binary file*.rbfFPGA configuration file
Diverse Reports---Diverse Reports---Report files in different formats
Software-Application-File*.elfSoftware application for NIOS II processor system


Download

Reference Design is only usable with the specified Quartus version. Do never use different versions of Quartus software for the same project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.

See also:


The Trenz Electronic FPGA Reference Designs are TCL-script based projects. To create a project, open a project or program a device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.

TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI. For currently Scripts limitations on Win OS and Linux OS see: Project Delivery - Intel devices → Currently limitations of functionality

  1. Open create_project_win.cmd/create_project_linux.sh:
  2. Select Board in "Board selection"
  3. Click on "Create project" button to create project
    1. (optional for manual changes) Select correct quartus installation path in "<project folder>/settings/design_basic_settings.tcl"
    Create and configure your Yocto Linux project, see Yocto KICKstart
  4. Copy the generated meta-<module> folder from <project name>/os/yocto/meta-<module> to the path/to/yocto/poky/ directory
  5. Follow the steps from Yocto KICKstart#Create a project for an Intel FPGA device without running the 'bitbake' command
  6. Add the generated bsp layer meta-<machine> to path/to/yocto/poky/build/conf/bblayers.conf with:

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    Info

    Note: The generated meta-<module> layer depends on the meta-altera layer (for more information see: Yocto KICKstart#Used source files), so you need to add both bsp layers to bblayers.conf

    Redefine the variable MACHINE with '<module>-<Board-Part-Short-Name>' in path/to//yocto/poky/build/conf/local.conf. The correct MACHINE name can be found in the #Hardware table.
    Also define the variables INITRAMFS_IMAGE_BUNDLE and INITRAMFS_IMAGE to generate a ram disk image.

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    sed -i '/^MACHINE/s/MACHINE/#MACHINE/g' conf/local.conf
    echo -e '\nMACHINE = "<module>-<Board-Part-Short-Name>"' >> conf/local.conf
    echo -e '\nINITRAMFS_IMAGE_BUNDLE = "1"' >> conf/local.conf
    echo -e 'INITRAMFS_IMAGE = "te-initramfs"' >> conf/local.conf

    Build the image with following command (the image recipes are located in meta-<module>/recipes-core/images/):

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Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Get prebuilt boot binaries

Note

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

  1. Run create_project_win.cmd/create_project_linux.sh
  2. Select Module in 'Board selection'
  3. Click on 'Export prebuilt files' button
    1. Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened

SD-Boot mode

Prepare SD card as follows for SD-Boot

Run following command to get the device name of the SD card  (e.g. /dev/sdx):

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lsblk
Insert SD card in the SD card reader, unmount and erase it
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sudo umount /dev/sdx
sudo sfdisk --delete /dev/sdx

Create required partitions on the SD card (partition 1: 50MB, FAT32 / partition 2: 2MB, a2) 

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sudo mkfs.vfat -F 32 -n boot /dev/sdb1

Copy the u-boot file to partition 2 of the SD card

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sync
  • Copy  zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/  via file manager to the partition 1 (named 'boot')  on SD card
  • Set Boot Mode to SD-Boot
    • Depends on Carrier, see carrier TRM
  • Insert SD-Card in the SD-Slot
  • QSPI-Boot mode

    Option for u-boot-with-spl.sfp on QSPI flash and zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and extlinux/extlinux.conf on SD card.

    Use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: #Get prebuilt boot binaries

  • Connect JTAG and power on carrier with module
  • Open path/to/intelFPGA_lite/21.1/embedded/Embedded_Command_Shell.bat ( Win OS)/path/to/intelFPGA_lite/21.1/embedded/embedded_command_shell.sh (Linux OS) from Intel SoC FPGA EDS
  • Run following commands:

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  • Copy  zimage-initramfs-<Yocto Machine Name>.bin, <Yocto Machine Name>.dtb, soc_system.rbf and the extlinux folder from path/to/_binaries_<Article Name>/boot_linux/ to SD card.
  • Set Boot Mode to QSPI-Boot
    • Depends on Carrier, see carrier TRM
  • Insert the SD card in the SD-Slot
  • Launch

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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Get prebuilt files

    Note

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    1. Run create_project_win.cmd/create_project_linux.sh
    2. Select Module in 'Board selection'
    3. Click on 'Export prebuilt files' button
      1. Folder <project folder>/_binaries_<Article Name> with subfolder programming_files will be generated and opened

    QSPI

    1. Connect JTAG and power on carrier with module
    2. Open create_project_win.cmd/create_project_linux.sh
    3. Select correct board in "Board selection"
    4. Click on "Program device" button
      1. if prebuilt files are available: select "Program prebuilt file"
      2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
      3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
    5. Click on "Start program device" button

    JTAG

    Not used on this example.

    Usage

    1. Prepare HW like described on section TEI0050 Intel Test Board
    2. Connect UART USB (most cases same as JTAG)

    UART

    1. Open Serial Console (e.g. PuTTY)
      1. select COM Port

        Info

        Win OS: see device manager

        Linux OS: see  dmesg | grep tty  (UART is *USB1)


      2. Speed: 115200
    2. Press reset button S1
    3. Press user button S2 to toggle between different LED sequences
    4. Console output depends on used Software project, see Software Design - SDK#Application

    System Design - Quartus

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    Note:

    • Description of Block Design - Project, Block Design - Platform Designer, ... Block Design Pictures from Export...

    Block Design

    The block designs may differ depending on the assembly variant.

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    Software Design - SDK

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    Note:
    • optional chapter separate

    • sections for different apps

    Application

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    ----------------------------------------------------------

    General Example:

    hello_tei0006

    Hello TEI0006 is a Hello World example as endless loop instead of one console output.

    Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

    hello_tei0050

    'hello_tei0050' is a Hello World example as endless loop instead of one console output.

    QSPI

    1. Connect JTAG and power on carrier with module
    2. Open create_project_win.cmd/create_project_linux.sh
    3. Select correct board in "Board selection"
    4. Click on "Program device" button
      1. if prebuilt files are available: select "Program prebuilt file"
      2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
      3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
    5. Click on "Start program device" button

    JTAG

    Not used on this example.

    Usage

    1. Prepare HW like described on section TEI0050 Intel Test Board
    2. Connect UART USB (most cases same as JTAG)
    3. Connect your board to the network
    4. Power on PCB

    UART

    Open Serial Console (e.g. PuTTY)

    select COM Port

    Info

    Win OS: see device manager

    Linux OS: see  dmesg | grep tty  (UART is *USB1)

  • Speed: 115200
  • Press reset button
  • Console output depends on used Software project, see Software Design - SDK#Application
  • Linux Console:

    Login data:

    Info

    Note: Wait until Linux boot finished

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    Username: root
    Password: root

    You can use Linux shell now.

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    i2cdetect -y -r 1   (check I2C 1 Bus)
    dmesg | grep rtc    (RTC check)
    udhcpc              (ETH0 check)
    lsusb               (USB check)
  • ...
  • System Design - Quartus

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    Note:

    • Description of Block Design - Project, Block Design - Platform Designer, ... Block Design Pictures from Export...

    Block Design

    The block designs may differ depending on the assembly variant.

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    titleBlock Design - Project
    >>Project<<
    Scroll Title
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    >>Platform Designer<<

    HPS Interfaces

    Activated interfaces:

    TypeNoteDDR--EMAC0--EMAC1--GPIO0--GPIO1--GPIO2--I2C0--I2C1--QSPI--SDMMC--UART0--UART1--USB0--USB1--CAN0--CAN1--

    Software Design - SDK

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    • sections for different apps

    Application

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    ----------------------------------------------------------

    General Example:

    hello_tei0006

    Hello TEI0006 is a Hello World example as endless loop instead of one console output.

    Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/

    ...

    Software Design - Yocto

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    For Yocto installation and project creation, follow instructions from:

    U-Boot

    Start with Create a custom BSP layer for Intel SoC or FPGA#Configure u-boot

    File location: meta-<module>/recipes-bsp/u-boot/

    Changes:

    • No changes

    Device Tree

    U-boot Device Tree

    Code Block
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    #u-boot device_tree.dts
    / {
    };
    
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    #device_tree-u-boot.dts
    / {
    };
    

    Kernel Device Tree

    Code Block
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    titleExcerpts from test_board/os/yocto/meta-<module_series>/recipes-kernel/linux/files/dts/<module_series>_<Board_Part_Short_Name>.dts
    #kernel device_tree.dts
    / {
    };
    

    Kernel

    Start withCreate a custom BSP layer for Intel SoC or FPGA#Configure linux kernel

    File location: meta-<module>/recipes-kernel/linux/

    Changes:

    • No changes.

    Images

    Image recipe for minimal console image

    File location: meta-<module>/recipes-images/yocto/

    Image recipes:

    • te-image-minimal.bb: create minimal linux image
    • te-initramfs.bb: required for building an image with initial RAM Filesystem

    Added packages/recipes:

    • No packages/recipes

    Rootfs

    Used filesystem: Initial RAM Filesystem (initramfs)

    Appx. A: Change History and Legal Notices

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    Document Change History

    To get content of older revision  got to "Change History"  of this page and select older document revision number.

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      • Metadata is only used of compatibility of older exports


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    Description

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    typeFlat

    • change list
    --all

    Page info
    infoTypeModified users
    dateFormatyyyy-MM-dd
    typeFlat

    --


    Legal Notices

    Include Page
    IN:Legal Notices
    IN:Legal Notices




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