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Scroll Title
anchorTable_OBP_ADC
titleADC to PL interface PL and pins

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DesignatorSchematicPL PinNotes
U1

S0_CLK          

S0_CSN          

S0_OUT          

J18

J16

K18

3.3V Max Voltage on any pin.
U2

S5_CLK          

S5_CSN          

S5_OUT          

M21

T16

T17

3.3V Max Voltage on any pin.
U3

S1_CLK          

S1_CSN          

S1_OUT          

L18

J21

L19

3.3V Max Voltage on any pin.
U4

S6_CLK          

S6_CSN          

S6_OUT          

J22

K21

J20

3.3V Max Voltage on any pin.
U10

S2_CLK          

S2_CSN          

S2_OUT          

M22 

R21 

R20 

3.3V Max Voltage on any pin.
U11

S7_CLK          

S7_CSN          

S7_OUT          

L22 

M20 

M19 

3.3V Max Voltage on any pin.
U15

S3_CLK          

S3_CSN          

S3_OUT          

J17 

J15 

L17 

3.3V Max Voltage on any pin.
U16

S8_CLK          

S8_CSN          

S8_OUT          

M17 

N18 

N17 

3.3V Max Voltage on any pin.
U17

S4_CLK          

S4_CSN          

S4_OUT          

P17 

L21 

P18 

3.3V Max Voltage on any pin.
U19

S9_CLK          

S9_CSN          

S9_OUT          

K15 

P21 

P20 

3.3V Max Voltage on any pin.


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Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

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U8 Pin Signal NameConnected toSignal DescriptionNote

TX_CLK

ETH-TXCK        MIO16

RGMII Transmit Clock

-

TXD[0..3]

ETH-TXD0..3MIO17..20

RGMII Transmit Data

-

TX_CTRL

ETH-TXCTL       MIO21

RGMII Transmit Control

-

RX_CLK

ETH-RXCK        MIO22

RGMII Receive Clock

-

RXD[0..3]

ETH-RXD0..3MIO23..26

RGMII Receive Data

-

RX_CTRL

ETH-RXCTL       MIO27

RGMII Receive Control

-

MDC

ETH-MDCMIO52

Management data clock reference

-

MDIO

ETH-MDIOMIO53

Management data

-

RESETn

PHY-RST         MIO51, U18

Hardware reset. Active low.

Shared with U18 (RESETB) USB

MDIP[0..3] MDIN[0..3]

PHY_MDI0..3_P
PHY_MDI0..3_N		JP1

Media Dependent Interface

-

XTAL_IN

ETH-CLK         U9

Reference Clock Input

see also Clock Sources section

LED[0..1]

PHY_LED0..1FPGA BANK 33

LED output

-


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Scroll Title
anchorTable_OBP_USB
titleUSB PHY to Zynq SoC connections

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U18 Pin Signal NameConnected toSignal DescriptionNote

CLKOUT

OTG-CLK         MIO36ULPI Output Clock-

DATA[0..3]

OTG-DATA0..3MIO32..35

ULPI bi-directional data bus

-

DATA[4]

OTG-DATA4       MIO28ULPI bi-directional data bus -

DATA[5..7]

OTG-DATA5..7MIO37..39ULPI bi-directional data bus -

DIR

OTG-DIR         MIO29

Controls the direction of the data bus

-

STP

OTG-STP         MIO30

terminates transfers PHY input

-

NXT

OTG-NXT         MIO31

control data flow into and out of the PHY

-

RESETB

PHY-RST MIO51, U8reset and suspend the PHY. Active low.Shared with U8 (RESETn) Ethernet

DP

USB_OTG_D_PJP2-64

D+ pin of the USB cable

3.3V Voltage level

DM

USB_OTG_D_N     JP2-65

D- pin of the USB cable

3.3V Voltage level

ID

USB_OTG_ID      JP2-66ID pin of the USB cable3.3V Voltage level

CPEN

USB_VBUS_EN     JP2-67

Controls the external VBUS power switch

3.3V Voltage level

VBUS

USB_VBUS        JP2-68

For RVBUS connection

Max. voltage: 5.5V

REFCLK

OTG-RCLK        U14 

ULPI clock input

see also Clock Sources section


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Scroll Title
anchorTable_OBP_FTDI
titleUSB FTDI to Zynq SoC connections

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U39 Pin Signal NameConnected toSignal DescriptionNote
DPD_JTAG_PJ13-2USB Data Signal Plus3.3V Voltage level
DMD_JTAG_NJ13-3USB Data Signal Minus3.3V Voltage level
ADBUS0TCKJP2-8,
TCK_0 (FPGA PL BANK 0)		Clock Signal Output3.3V Voltage level.
MPSSE Mode
ADBUS1TDIJP2-11,
TDI_0 (FPGA PL BANK 0)		Serial Data Output3.3V Voltage level.
MPSSE Mode
ADBUS2TDOJP2-10,
TDO_0 (FPGA PL BANK 0)		Serial Data Input3.3V Voltage level.
MPSSE Mode
ADBUS3TMSJP2-7,
TMS_0 (FPGA PL BANK 0)		Output Signal Select3.3V Voltage level.
MPSSE Mode
BDBUS0UART_TX_OBU36-5Asynchronous serial TXDU36-3 Bus Switch pin connects later this signal to UART_RX_ZYNQ when UART_OB_DISABLE is low or floating.
BDBUS1UART_RX_OBU36-6Asynchronous serial RXDU36-2 Bus Switch pin connects later this signal to UART_TX_ZYNQ when UART_OB_DISABLE is low or floating.
OSCIOSCI
Oscillator input-
EECS, EECLK, EEDATAEECS, EECLK, EEDATAU40-1..3EEPROM interface-
-UART_OB_DISABLEJP1-11Enable signal of the FTDI-PS_UART Bus Switch U36.Active Low!.


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Power supply with minimum current capability of 3.0 A (TBD*) for system startup is recommended.

* TBD - To Be Determined

Power Consumption

Scroll Title
anchorTable_PWR_PC
titlePower Consumption

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Power Input PinTypical Current
+5.0VTBD*
+5.0V_VAAless than 250mA (TBD*)


* TBD - To Be Determined

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Scroll Title
anchorTable_TS_AMR
titlePS absolute Absolute maximum ratings

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SymbolsDescriptionMinMaxUnitReference
+5.0VMain Supply voltage from the carrier board-0.36.0VNCV6357 Datasheet
NCV6323 Datasheet
NCP160 Datasheet
+5.0V_VAAAnalog Supply voltage from the carrier board-0.36.0VNCP160 Datasheet
MIO 500I/O input voltage for MIO bank 500-0.43.85VXilinx DS187 Datasheet
MIO 501I/O input voltage for MIO bank 501-0.42.35VXilinx DS187 Datasheet
PL HRI/O input voltage for HR banks-0.43.85VXilinx DS187 Datasheet
ADCx_P/NI/O input voltage for ADCs analog inputs-0.33.63VNCD98011 Datasheet


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