| U8 Pin | Signal Name | Connected to | Signal Description | Note |
|---|
| 53 TX_CLK | ETH-TXCK | MIO1650 | RGMII Transmit Clock | - |
TXD[0..3] | ETH-TXD0 | MIO17 | ..3 | MIO17..20 | RGMII Transmit Data
| - |
TX_CTRL 51 | ETH-TXD1 TXCTL | MIO18MIO2154 | RGMII Transmit Control | ETH-TXD2 | MIO19 | |
RX_CLK | ETH-RXCK | 55 | ETH-TXD3 | MIO20MIO2256 | RGMII Receive Clock | ETH-TXCTL | MIO21 | 46 | ETH-RXCK | MIO22 | 44 | ETH-RXD0 | MIO23 | 45 | ETH-RXD1 | MIO24 | 47 | ETH-RXD2 | MIO25 | 48 | ETH-RXD3 | MIO26 | 46 | ETH-RXCK | - |
RXD[0..3] | ETH-RXD0..3 | MIO23..26 | RGMII Receive Data | - |
RX_CTRL | ETH-RXCTL | MIO27 | RGMII Receive Control | - |
MDC | ETH-MDC | MIO52 | Management data clock reference | - |
MDIO | ETH-MDIO | MIO53 | Management data | - |
RESETn | PHY-RST | MIO51, U18 | Hardware reset. Active low. | Shared with U18 (RESETB) USB |
MDIP[0..3] MDIN[0..3] | PHY_MDI0..3_P
PHY_MDI0..3_N | JP1 | Media Dependent Interface | - |
XTAL_IN | ETH-CLK | U9 | Reference Clock Input | see Clock Sources section |
LED[0..1] | PHY_LED0..1 | FPGA BANK 33 | LED output MIO27 |
|