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| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U7 Pin | Notes |
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| MIO1 | SPI-CS | C2 | - | | MIO3 | SPI-DQ1/M1 | D2 | - | | MIO4 | SPI-DQ2/M2 | C4 | - | | MIO2 | SPI-DQ3/M3 | D4 | - | | MIO5 | SPI-DQO/M0 | D3 | - | | MIO6 | SPI-SCK/M4 | B2 | - |
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EEPROM
MAC-Address EEPROM
A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.
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| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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| D3 | Green | DONE (FPGA BANK 0) | Low | When LED is OFF, the FPGA is programmed. | | D4 | RGB | MIO11 (LED1_R)
MIO12 (LED1_G)
MIO13 (LED1_B) | High | - | | D5 | RGB |
| High |
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Switches
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Connected to | Active Level | Function | Note |
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