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| Scroll Title |
|---|
| anchor | Table_OBP_SPI |
|---|
| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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| MIO Pin | Schematic | U7 Pin | Notes |
|---|
| MIO1 | SPI-CS | C2CS# | - | | MIO3 | SPI-DQ1/M1 | D2SO/IO1 | - | | MIO4 | SPI-DQ2/M2 | C4WP#/IO2 | - | | MIO2 | SPI-DQ3/M3 | D4HOLD#/IO3 | - | | MIO5 | SPI-DQO/M0 | D3SI/IO0 | - | | MIO6 | SPI-SCK/M4 | B2SCK | - |
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EEPROM
MAC-Address EEPROM
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| Scroll Title |
|---|
| anchor | Table_OBP_ETH |
|---|
| title | Ethernet PHY to Zynq SoC connections |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| U8 Pin | Signal Name | Connected to | Signal Description | Note |
|---|
TX_CLK | ETH-TXCK | MIO16 | RGMII Transmit Clock | - | TXD[0..3] | ETH-TXD0..3 | MIO17..20 | RGMII Transmit Data
| - | TX_CTRL | ETH-TXCTL | MIO21 | RGMII Transmit Control | - | RX_CLK | ETH-RXCK | MIO22 | RGMII Receive Clock | - | RXD[0..3] | ETH-RXD0..3 | MIO23..26 | RGMII Receive Data | - | RX_CTRL | ETH-RXCTL | MIO27 | RGMII Receive Control | - | MDC | ETH-MDC | MIO52 | Management data clock reference | - | MDIO | ETH-MDIO | MIO53 | Management data | - | RESETn | PHY-RST | MIO51, U18 | Hardware reset. Active low. | Shared with U18 (RESETB) USB | MDIP[0..3] MDIN[0..3] | PHY_MDI0..3_P
PHY_MDI0..3_N | JP1 | Media Dependent Interface | - | XTAL_IN | ETH-CLK | U9 | Reference Clock Input | see also Clock Sources section | LED[0..1] | PHY_LED0..1 | FPGA BANK 33 | LED output | - |
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USB 2.0 ULPI transceiver
USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution with full OTG support.
- Part number: USB3320C-EZK
- Supply voltage: 1.8V and 3.3V.
- Temperature: Industrial Range -40°C to +85°C.
| Scroll Title |
|---|
| anchor | Table_OBP_USB |
|---|
| title | USB PHY to Zynq SoC connections |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| U18 Pin | Signal Name | Connected to | Signal Description | Note |
|---|
| 1 CLKOUT | OTG-CLK | MIO36 | ULPI Output Clock | - | DATA[0..3] | OTG-DATA0 DATA0..3 | MIO32..35 | ULPI bi-directional data bus | - | DATA[4] | 4 | OTG-DATA1 | MIO33 | 5 | OTG-DATA2 DATA4 | MIO34 | 6 | OTG-DATA3 | MIO35 | 7 | OTG-DATA4 | MIO28 | MIO28 | ULPI bi-directional data bus | - | DATA[5..7] | OTG-DATA5..7 | MIO37..39 | ULPI bi-directional data bus | - | DIR | 9 | OTG-DATA5 | MIO37 | 10 | OTG-DATA6 | MIO38 | 13 | OTG-DATA7 | MIO39 | 31 | OTG-DIR | MIO29 | Controls the direction of the data bus | - | STP 29 | OTG-STP | MIO30 | terminates transfers PHY input | - | NXT 2 | OTG-NXT | MIO31 | control data flow into and out of the PHY | - | RESETB 27 | PHY-RST | MIO51, U8 | reset and suspend the PHY. Active low. | Shared with U8 (RESETn) Ethernet | | 18 DP | USB_OTG_D_P | JP2-64 | D+ pin of the USB cable | 3.3V Voltage level | DM 19 | USB_OTG_D_N | JP2-65 | D- pin of the USB cable | 3.3V Voltage level | ID 23 | USB_OTG_ID | JP2-66 | ID pin of the USB cable | 3.3V Voltage level | CPEN 17 | USB_VBUS_EN | JP2-67 | Controls the external VBUS power switch | 3.3V Voltage level | VBUS 22 | USB_VBUS | JP2-68 | For RVBUS connection | Max. voltage: 5.5V | REFCLK 26 | OTG-RCLK | U14 | ULPI clock input | see also Clock Sources section |
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