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  • Part number: NCD98011XMXTAG
  • Analog supply and ADC reference voltage (VCC): 3.3V (1.65V – 3.6V).
  • Digital I/O supply voltage (VDD): 3.3V (1.65V – 3.6V).
  • Differential analog inputs: 1 per ADC.
  • Full−Scale Analog input range: Input Voltage Span: +VCC max Vppd, -VCC min Vppd, (VCM to VCC/2).
  • Absolute Voltage Range Vinp or Vinn to GND: VCC + 0.1V
  • Vpp.Sampling rate: 2 MSPS max.
  • SNR: 70dB @1KHz fIN.
  • THD: -80dB @1KHz fIN.
  • Junction Temperature: Range -40°C to +125°C.

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Scroll Title
anchorTable_OBP_INADC
titleADC Analog interface and pins

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DesignatorSchematicB2B JP1 pinNotes

All the diigital signals are connected to PL Bank 34 as follows:

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anchorTable_OBP_ADC
titleADC interface PL and pins
U1ADC0_P
ADC0_N		106 - 107 
U2

ADC5_P
ADC5_N

52 - 53 
U3

ADC1_P
ADC1_N

46 - 47 
U4

ADC6_P
ADC6_N

115 - 116 
U10

ADC2_P
ADC2_N

109 - 110 
U11

ADC7_P
ADC7_N

55 - 56 
U15

ADC3_P
ADC3_N

49 - 50 
U16

ADC8_P
ADC8_N

118 - 119 
U17

ADC4_P
ADC4_N

112 - 113 
U19

ADC9_P
ADC9_N

58 - 59 


All the diigital signals are connected to PL Bank 34 as follows:

Scroll Title
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titleADC interface PL and pins

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Clock Sources

Scroll Title
anchorTable_OBP_CLK
titleOscillators

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U6MHz
DesignatorDescriptionSchematicFrequencyPL PinNoteNotes
U1


U2


-U3
U9Ethernet PHY Reference Clock Input25MHz-
U14Ethernet PHY Reference Clock Input52MHz-
U41MHz-

Ethernet




U4


U10


U11


U15


U16


U17


U19



Clock Sources

Scroll Title
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titleOscillators

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DesignatorDescriptionFrequencyNote
U6
MHz-
U9Ethernet PHY Reference Clock Input25MHz-
U14Ethernet PHY Reference Clock Input52MHz-
U41
MHz-


Ethernet

Scroll Title
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titleEthernet PHY to Zynq SoC connections

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U8 Pin Signal NameConnected toSignal DescriptionNote

TX_CLK

ETH-TXCK        MIO16

RGMII Transmit Clock

-

TXD[0..3]

ETH-TXD0..3MIO17..20

RGMII Transmit Data

-

TX_CTRL

ETH-TXCTL       MIO21

RGMII Transmit Control

-

RX_CLK

ETH-RXCK        MIO22

RGMII Receive Clock

-

RXD[0..3]

ETH-RXD0..3MIO23..26

RGMII Receive Data

-

RX_CTRL

ETH-RXCTL       MIO27

RGMII Receive Control

-

MDC

ETH-MDCMIO52

Management data clock reference

-

MDIO

ETH-MDIOMIO53

Management data

-

RESETn

PHY-RST         MIO51, U18

Hardware reset. Active low.

Shared with U18 (RESETB) USB

MDIP[0..3] MDIN[0..3]

PHY_MDI0..3_P
PHY_MDI0..3_N		JP1

Media Dependent Interface

-

XTAL_IN

ETH-CLK         U9

Reference Clock Input

see also Clock Sources section

LED[0..1]

PHY_LED0..1FPGA BANK 33

LED output

-


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Power supply with minimum current capability of xx A 3.0 A (TBD) for system startup is recommended.

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Scroll Title
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titlePower Consumption

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Power Input PinTypical Current
VIN+5.0VTBD*
+5.0V_VAAless than 250mA (TBD)


* TBD - To Be Determined

Power Distribution Dependencies

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Scroll Title
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titleModule power rails.

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Power Rail Name

B2B Connector

JM1

JP1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3

JP2 Pin

DirectionNotes

Bank Voltages

+5.0V1, 2, 31, 2, 3InputMain Supply voltage from the carrier board
+5.0V_VAA43, 44-InputAnalog Supply voltage from the carrier board
+3.3V (VREF_JTAG)-5OutputJTAG reference voltage.


Bank Voltages

Scroll Title
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titleZynq SoC bank voltages.

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Scroll Title
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titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes
PS BANK 500VCCO_MIO0_500+3.3V-
PS BANK 501

VCCO_MIO0_501

+1.8V   -
PS BANK 502VCCO_DDR_502+1.5V-
PL BANK 0 HRVCCO_0+3.3V-
PL BANK 13 HRVCCO_13+3.3V-
PL BANK 33 HRVCCO_33+3.3V

-

PL BANK 34 HRVCCO_34+3.3V

-

PL BANK 35 HRVCCO_35+3.3V-



Board to Board Connectors

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