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Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

B2B Connector

Notes
TMSJP2-73.3V Voltage level. Also Connected to U39 (FTDI)
TDIJP2-113.3V Voltage level. Also Connected to U39 (FTDI)
TDOJP2-103.3V Voltage level. Also Connected to U39 (FTDI)
TCK

JP2-8

3.3V Voltage level. Also Connected to U39 (FTDI)

VREF_JTAGJP2-5Module Vout


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Scroll Title
anchorTable_SIP_MIOs
titleMIOs pins

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MIO PinConnected toB2BNotes
15UART_TX_ZYNQJP1-703.3V Voltage level. Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High".
14UART_RX_ZYNQJP1-713.3V Voltage level. Also Connected to U36-3. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High".


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Scroll Title
anchorTable_OBP
titleOn board peripherals

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Chip/InterfaceDesignatorNotes
DDR3 SDRAMU12, U13-
Quad SPI FlashU7-
MAC EEPROMU24-
General Purpose EEPROMU21-
SAR ADCsU1, U2, U3, U4, U10, U11, U15, U16, U17, U19-
Clock SourcesU6, U9, U14, U41-
Gigabit Ethernet PHYU8-
USB 2.0 ULPI transceiverU18-
FTDI USB 2.0 to UART/JTAGU39-
LEDsD3, D4, D5-
SwitchesS1, S2, S3-


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Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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MIO PinSchematicU7 PinNotes
MIO1SPI-CSC2-
MIO3SPI-DQ1/M1D2-
MIO4SPI-DQ2/M2C4-
MIO2SPI-DQ3/M3D4-
MIO5SPI-DQO/M0D3-
MIO6SPI-SCK/M4B2-


EEPROM

MAC-Address EEPROM

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Scroll Title
anchorTable_OBP_CLK
titleOscillators

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DesignatorDescriptionFrequencyNote
U6
MHz-
U9Ethernet PHY Reference Clock Input25MHz-
U14Ethernet PHY Reference Clock Input52MHz-
U41
MHz-


Ethernet

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

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U8 Pin Signal NameConnected toSignal DescriptionNote

TX_CLK

ETH-TXCK        MIO16

RGMII Transmit Clock

-

TXD[0..3]

ETH-TXD0..3MIO17..20

RGMII Transmit Data

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TX_CTRL

ETH-TXCTL       MIO21

RGMII Transmit Control

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RX_CLK

ETH-RXCK        MIO22

RGMII Receive Clock

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RXD[0..3]

ETH-RXD0..3MIO23..26

RGMII Receive Data

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RX_CTRL

ETH-RXCTL       MIO27

RGMII Receive Control

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MDC

ETH-MDCMIO52

Management data clock reference

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MDIO

ETH-MDIOMIO53

Management data

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RESETn

PHY-RST         MIO51, U18

Hardware reset. Active low.

Shared with U18 (RESETB) USB

MDIP[0..3] MDIN[0..3]

PHY_MDI0..3_P
PHY_MDI0..3_N		JP1

Media Dependent Interface

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XTAL_IN

ETH-CLK         U9

Reference Clock Input

see also Clock Sources section

LED[0..1]

PHY_LED0..1FPGA BANK 33

LED output



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Scroll Title
anchorTable_OBP_USB
titleUSB PHY to Zynq SoC connections

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U?? Pin U18 Pin Signal NameConnected toSignal DescriptionNote
1OTG-CLK         MIO36

3OTG-DATA0       MIO32

4OTG-DATA1       MIO33

5OTG-DATA2       MIO34

6OTG-DATA3       MIO35

7OTG-DATA4       MIO28

9OTG-DATA5       MIO37

10OTG-DATA6       MIO38

13OTG-DATA7       MIO39

31OTG-DIR         MIO29

29OTG-STP         MIO30

2OTG-NXT         MIO31

27PHY-RST MIO51, U8
Shared with U8 (RESETn) Ethernet
18USB_OTG_D_PJP2-64

19USB_OTG_D_N     JP2-65

23USB_OTG_ID      JP2-66

17USB_VBUS_EN     JP2-67

22USB_VBUS        JP2-68

26OTG-RCLK        U14 
see also Clock Sources section


FTDI USB 2.0 to UART/JTAG

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