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| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
|---|
| title | General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| B2B Connector | Interfaces | Number of I/O | Notes |
|---|
J1
| User I/O | 48 singel ended, 24 differential | Connected to Bank 13 | | 4 Single ended | MIO10-13 | | CANH , CANL | 2 single ended | MIO8, MIO9 | J2
| User I/O | 22 singel ended, 11 differential |
| | 38 single ended | MIO16-53 | | SoM Control Signals | 5 | RESET, RST_OUT, BOOT_R, | | JTAG Interface | 4 | TCK , TDO, TDI, TMS | J3
| User I/O | 20 Single ended, 10 differential
| Connected to Bank 35 | | 34 single ended, 17 differential | Connected to Bankd 33 | | Ethernet 1 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 | | Ethernet 2 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 |
|
On-board Connector
| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
|---|
| title | General PL I/O to B2B connectors information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| B2B Connector | Interfaces | Number of I/O | Notes |
|---|
J5
| User I/O | 48 singel ended, 24 differential | Connected to Bank 13 | | 34 single ended, 17 differential | Connected to Bank 33 | J6
| User I/O | 42 singel ended, 21 differential |
| | 27 single ended | MIO16-39 + MIO 51-53 | | 4 single ended | MIO10-13 | | SoM Control Signals | 3 | RESET, RST_OUT, BOOT_R | | JTAG Interface | 4 | TCK , TDO, TDI, TMS | CANH , CANL | 2 Single ended | MIO8 , MIO9 |
|
JTAG Interface
JTAG access to the Xilinx XXXXXXX FPGA through B2B connector JM2.
| Scroll Title |
|---|
| anchor | Table_SIP_JTG |
|---|
| title | JTAG pins connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | B2B Pin |
|---|
| TMS | J2-12 | | TDI | J2-10 | | TDO | J2-8 | | TCK | J2-6 |
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On-board Peripherals
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
...