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Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
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        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
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        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


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Table of Contents

Table of Contents

Overview

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Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

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    • Note:
  • ...
  • ....
  • ....

Block Diagram

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titleTE0728 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


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titleTEXXXX main components


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  1. MByte DDR3 SDRAM, Cypress DDR3 Memory, U
  2. Xilinx  ,U2
  3. 100 MBit Ethernet transceiver, U
  4. Standard Clock Oscillators @X MHz , U
  5.  Low Dropout Linear Regulator, U
  6. Real Time Clock, Micro Crystal @X MHz,, U
  7.  MBit Ethernet transceiver, U
  8. Kbit I2C EEPROM, U
  9. MByte QSPI Nor Flash memory, U
  10. Standard Clock Oscillators @X MHz , U
  11. CAN Tranceiver, U
  12. B2B connector  , JM2
  13. B2B connector , JM3
  14. B2B connector , JM1
  15. User LED

Initial Delivery State

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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Quad SPI Flash


Not Programmed

DDR3 SDRAM

Not Programmed

RTC

Not Programmed


Control Signals

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  • Overview of Boot Mode, Reset, Enables,

Boot Process

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titleBoot process.

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MODE Signal State

Boot Mode

High or open

QSPI





Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:


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titleGeneral PL I/O to B2B connectors information

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
































JTAG Interface

JTAG access to the Xilinx XXXXXXX FPGA through B2B connector JM2.

Scroll Title
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titleJTAG pins connection

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JTAG Signal

B2B Pin











On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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titleOn board peripherals

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Chip/InterfaceICPS7 PeripheralNotes






















Quad SPI Flash Memory

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.


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titleQuad SPI interface MIOs and pins

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MIO PinSchematicU13 PinNotes


























RTC


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titleI2C interface MIOs and pins

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MIO PinSchematicU7 PinNotes

SDA


SCL


EEPROM

Scroll Title
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titleI2C EEPROM interface MIOs and pins

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MIO PinSchematicUxx PinNotes

SDA


SCL



LEDs

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titleOn-board LEDs

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SchematicColorConnected toActive LevelIO Standard

















DDR3 SDRAM

The TE0728 SoM has XXX GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

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titleEthernet PHY to Zynq SoC connections

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SchematicETH1ETH2PullupNotes
CTREF



TD+



TD-



RD+



RD-



LED1



LED2



LED3



POWERDOWN/INT



RESET_N





CAN Transceiver


Scroll Title
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titleCAN Tranciever interface MIOs

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MIO PinSchematicU16 PinNotes

D


R


Low Quiescent Current Programmable Delay Supervisory Circuit


Low Dropout Linear Regulator


Clock Sources

Scroll Title
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titleOsillators

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ICDescriptionFrequencyUsed as

MEMS OscillatorMHz

MEMS OscillatorMHz

RTC (internal oscillator)KHz



Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

Scroll Title
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titlePower Consumption

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Power Input PinTypical Current
VINTBD*



* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title
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titlePower Distribution


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Power-On Sequence

Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


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Voltage Monitor Circuit


Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

Scroll Title
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titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)

    Operating Temperature:-55°C ~ 125°C
    Current Rating: 2.6A per ContactNumber of Positions: 80
    Number of Rows: 2

Absolute Maximum Ratings

Processing System(PS)

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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit
VCCPINTPS internal logic supply voltage-0.51.1V
VCCPAUXPS auxiliary supply voltage-0.52.0V
VCCPLLPS PLL supply-0.52.0V
VCCO_DDRPS DDR I/O supply voltage-0.52.0V
VPREFPS input reference voltage-0.52.0V
VCCO_MIO0PS MIO I/O supply voltage for HR I/O banks-0.53.6V
VCCO_MIO1PS MIO I/O supply voltage for HR I/O banks1.713.45V



Programmable Logic(PL)

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titlePL absolute maximum ratings

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SymbolsDescriptionMinMaxUnit
VCCINTPL internal logic supply voltage-0.51.1V
VCCPAUXPL auxiliary supply voltage-0.52.0V
VCCPLLPL PLL supply-0.51.1V
VPREFPL input reference voltage-0.52.0V
VCCOPL supply voltage for HR I/O banks-0.53.6V
VINI/O input voltage for HR I/O banks1.713.45V



Technical Specifications

Absolute Maximum Ratings

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titleModule absolute maximum ratings.

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-40125°CSee Xilinx DS187 datasheet.



Recommended Operating Conditions

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.


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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-65150°CSee Xilinx DS187 datasheet.
CAN Transceiver Temperature-40125°CSee Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory-4085°CSee Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature-4095°C

See Nanya NT5CC256M16CP-DIA datasheet.




Physical Dimensions

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titlePhysical dimensions drawing

  • Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 7 mm.

  • PCB thickness: 1.6 mm.

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titlePhysical Dimension



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Variants Currently In Production

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titleTrenz Electronic Shop Overview

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Trenz shop TE0728 overview page
English pageGerman page



Revision History

Hardware Revision History

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titleHardware Revision History

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DateRevisionNotePCNDocumentation Link
-01Prototypes--







Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History


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  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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titleDocument change history.

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DateRevisionContributorDescription

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  • change list

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all

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  • --


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