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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| B2B Connector | Interfaces | Number of I/O | Notes |
|---|
J5
| User I/O | 48 singel ended, 24 differential | Connected to Bank 13 | | 34 single ended, 17 differential | Connected to Bank 33 | J6
| User I/O | 42 singel ended, 21 differential |
| | 27 single ended | MIO16... MIO39 + MIO 51-53 | | 4 single ended | MIO10-13 | | SoM Control Signals | 3 | RESET, RST_OUT, BOOT_R | | JTAG Interface | 4 | TCK , TDO, TDI, TMS | CANH , CANL | 2 single ended | MIO8 , MIO9 |
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JTAG Interface Base
JTAG access to the TE0728 Trenz Module through B2B connector J2.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Connected toJTAG Signal | B2B Pin | Note |
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| A | MIO52 | J2-15 | UART | | B | MIO53 | J2-16 |
| | C | TMS | J2-12 | JTAG interface signal | | D | TDI | J2-10 | JTAG interface signal | | F | TDO | J2-8 | JTAG interface signal | | H | TCK | J2-6 | JTAG interface signal |
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JTAG mode
The DIP-switch S2 on JTAG interface is connected to JTAGEN.
| Scroll Title |
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| anchor | Table_SIP_JTG_Mode |
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| title | JTAG pMode |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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|
| S2 | ON | OFF | Default | Description |
|---|
| 1 | Normal mode | Adapter board CPLD update mode | ON | Update Mode JTAG access to SC CPLD only | | 2 | Do not use (illegal setting) | Normal mode | OFF | Must be in OFF state always. | | 3 | VIO connected to 3.3V | Power VIO from pin header J2 | OFF | User I/O Voltage | | 4 | Power 3.3V from USB | Power 3.3V from pin header J2 | OFF | Power on-board peripherals (FTDI chip & SC CPLD, ...) |
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On-board Peripherals
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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