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Scroll Title
anchorFigure_OV_BD
titleTE0728 block diagram


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Main Components

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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J5

User I/O48 singel ended, 24 differentialConnected to Bank 13
34 single ended, 17 differentialConnected to Bank 33
J6

User I/O42 singel ended, 21 differential
27 single endedMIO16-39 + MIO 51-53
4 single endedMIO10-13
SoM Control Signals3RESET, RST_OUT, BOOT_R
JTAG Interface4TCK , TDO, TDI, TMS

CANH , CANL

2
Single
single endedMIO8 , MIO9



JTAG Interface

JTAG access to the Xilinx XXXXXXX FPGA through B2B connector JM2.

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

SD Card Socket

PS7 Peripheral
Scroll Title
anchorTable_OBP
titleOn board peripherals

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SignalsConnected toB2B
Chip/InterfaceIC
Notes

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CD/DAT3MIO45J2-31
CMDMIO41J2-29
CLKMIO40_CLKJ2-34
DAT0MIO42J2-37
DAT1MIO43J2-40
DAT2MIO44J2-32
CDMIO46J2-35
WPMIO47J2-33



RJ45 Connector


Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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cellHighlightingtrue

MIO Pin
Signal
SchematicU13 Pin
B2BSignalB2BNotes
ETH1_TD+J3-58ETH2_TD+J3-28Transfer
ETH1_TD-J3-56ETH2_TD-J3-26
ETH1_RD+J3_52ETH2_RD+J3-22Receive
ETH1_RD-J3-50ETH2_RD-J3-20
ETH1_CTREFJ3_57ETH2_CTREFJ3-25
ETH1_LED1J3-55ETH2_LED1J3-23Yellow - Activity
ETH1_LED3J3-51ETH2_LED3J3-19Green - Link
Notes



LEDs

Scroll Title
anchorTable_OBP_LED
titleOn-board LEDs

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SchematicColorConnected toActive LevelIO Standard
















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