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| anchor | Figure_1 |
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| title | Figure 1: TE0782-02 block diagram |
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Main Components
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| anchor | Figure_2 |
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| title | Figure 2: TE0782-02 main components |
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Fotos müssen ausgetauscht werden, hier noch TE0782 als Platzhalter
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| anchor | Figure_3 |
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| title | Figure 3: TE0782-02 Power Distribution Diagram |
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See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0782 module.
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| anchor | Figure_4 |
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| title | Figure 4: TE0782-02 Power-on Sequence Diagram |
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Voltage Monitor Circuit
The voltages '1V' and '3.3V' are monitored by the voltage monitor circuit U4, which generates the PS_POR_RST reset signal if monitored voltages have transient interruptions. The reset signal is connected to the SC CPLD U14 and forwarded to the Zynq MIO bank 500 'PS_POR' pin:
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| anchor | Figure_5 |
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| title | Figure 5: TE0784-01 Voltage Monitor Circuit |
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Power Rails
| Power Rail Name on B2B Connector | J1 Pins | J2 Pins | J3 Pins | Direction | Notes |
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| VIN | - | 165, 166, 167, 168 | - | Input | external power supply voltage |
| C3.3V | - | 147, 148 | - | Input | external 3.3V power supply voltage |
| 3.3V | - | 111, 112, 123, 124, 135 136 169, 170, 171, 172 | - | Output | internal 3.3V voltage level |
| 1.8V | 169, 170, 171, 172 | - | - | Output | internal 1.8V voltage level |
| VCCIO_10 | - | - | 99, 100 | Input | high range I/O bank voltage |
| VCCIO_11 | - | - | 159, 160 | Input | high range I/O bank voltage |
| VCCIO_12 | - | 159, 160 | - | Input | high range I/O bank voltage |
| VCCIO_13 | - | 99, 100 | - | Input | high range I/O bank voltage |
| VCCIO_33 | 99, 100 | - | - | Input | high performance I/O bank voltage |
| VCCIO_34 | 159, 160 | - | - | Input | high performance I/O bank voltage |
| VBAT_IN | - | - | 124 | Input | backup battery voltage |
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