Page History

<!--
Template Revision 1.68
(HTML comments will be not displayed in the document, no need to remove them. For Template/Skeleton changes, increase Template Revision number. So we can check faster, if the TRM style is up to date).
-->

<!--
General Notes:
If some section is CPLD firmware dependent, make a note and if available link to the CPLD firmware description. It's in the TE shop download area in the corresponding module -> revision -> firmware folder.
-->

<!--
General Notes:
Designate all graphics and pictures with a number and a description. For example "Figure 1: TE07xx-xx Block Diagram" or "Table 1: Initial delivery state". "Figure x" and "Table x" have to be formatted to bold.  
-->

<!--
Link to the base folder of the module (remove de/ or en/ from the URL): for example:
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0703/
  -->

Overview

The Trenz Electronic TE0784 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC XC7Z045-2FFG900I.

These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are rugged for industrial applications.

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

<!--
Use short link the Wiki Ressource page: for example:
http://trenz.org/te0782-info
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects
  -->

Refer to http://trenz.org/te0784-info for the current online version of this manual and other available documentation.

Key Features

• Xilinx Zynq-7000 XC7Z045 SoC
• Rugged for shock and high vibration
• Large number of configurable I/Os are provided via rugged high-speed stacking strips
• Dual ARM Cortex-A9 MPCore
  • 1 GByte RAM (32-Bit wide DDR3)
  • 32 MByte QSPI Flash memory
  • 2 x Hi-Speed USB2 ULPI transceiver PHY
  • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64 GByte)
• 2 x MAC-address EEPROMs
• Optional 2x 64 MByte HyperFLASH or 2x 8 MByte HyperRAM (max 2x 32 MByte HyperRAM)
• Temperature compensated RTC (real-time clock)
• Si5338A programmable quad PLL clock generator for GTX transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver
  • 2x GT transceiver clock inputs
  • 254 FPGA I/O's (125 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED

Assembly options for cost or performance optimization available upon request.

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

<!--
Rules for all diagrams:
1. All diagrams are wrapped in the "Scroll Title" macro.
	- The title has to be named with the diagrams name
	- The anchor has the designation figure_x, whereby x is the number of the diagram

2. The Draw.IO diagram has to be inserted in the "Scroll Ignore" macro
	- Border has to be switched off in the macro edit
	- Toolbar has to be hidden in the macro edit

3. A PNG Export of the diagram has to be inserted in the "Scroll Only" macro 

The workaround with the additional PNG of the diagram is necessary until the bug of the Scroll PDF Exporter, which cuts diagram to two pages, is fixed.


IMPORTANT NOTE: In case of copy and paste the TRM skeleton to a new Wiki page, delete the Draw.IO diagrams and the PNGs, otherwise due to the linkage of the copied diagrams every change in the TRM Skeleton will effect also in the created TRM and vice versa!

See page "Diagram Drawing Guidelines" how to clone an existing diagram as suitable template for the new diagram! 

   -->

Main Components

1. Xilinx Zynq-7000 SoC, U1
2. Lattice Semiconductor MachXO2 1200HC CPLD, U14
3. 4Gbit DDR3L SDRAM, U19
4. 4Gbit DDR3L SDRAM, U10
5. I²C voltage translator, U25
6. Intersil ISL12020MIRZ Real Time Clock, U17
7. Microchip USB3320C USB PHY transceiver, U4
8. Microchip USB3320C USB PHY transceiver, U8
9. SiTime SiT8008 52.000000 MHz oscillator, U7
10. 32 MByte QSPI Flash memory, U38
11. SiTime SiT8008 33.333333 MHz oscillator, U61
12. SI5338A programmable quad PLL clock generator, U2
13. SiTime SiT8008 25.000000 MHz oscillator, U3
14. TPS74801 LDO @1.5V, U23
15. LT quad 4A PowerSoC DC-DC converter (@1.0V), U13
16. LT quad 4A PowerSoC DC-DC converter (@3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT), U16
17. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
18. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3
19. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
20. Marvell Alaska 88E1512 Gigabit Ethernet PHY, 20
    
21. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
22. Micron Technology 4 GByte eMMC, U15
23. Microchip 128Kbit I²C EEPROM, U26
24. Microchip 2Kbit I²C MAC EEPROM, U24
25. Microchip 2Kbit I²C MAC EEPROM, U22
26. TPS51206 DDR reference voltage and termination regulator, U6
27. TPS799 LDO @1.8V_MGT, U5
28. SiTime SiT8008 25.000000 MHz oscillator, U11

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

4 of the 7 boot mode strapping pins (MIO2 ... MIO8) of the Xilinx Zynq-7000 SoC device are hardware programmed on the board, 3 of them are set by the SC CPLD firmware. The boot strapping pins are evaluated by the Zynq device soon after the 'PS_POR' signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0782 board is programmed in the SC CPLD firmware to boot initially from the on-board QSPI Flash memory U38. See section Bootmode in the TE0782 SC CPLD reference Wiki page.

The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq-7000 device.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq-7000 SoC's I/O banks signals connected to the B2B connectors:

Table 2: General overview of board to board I/O signals

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq-7000 SoC used on the TE0782 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: MGT lanes

There are 2 clock sources for the GTX transceivers. MGT_CLK1 and MGT_CLK4 are connected directly to B2B connector J3 and J1, so the clock can be provided by the carrier board. Clocks MGT_CLK0, MGT_CLK3, MGT_CLK5 and MGT_CLK6 are provided by the on-board clock generator (U2). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector J3.

Table 5: Zynq JTAG interface signals

JTAG access to the LCMXO2-1200HC System Controller CPLD U14 is provided through B2B connector J3.

Table 6: System Controller CPLD JTAG interface signals

Pin J3-136 'JTAGENB' of B2B connector J3 is used to access the JTAG interface of the SC CPLD. Set high to program the System Controller CPLD via JTAG interaface.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Table 7: System Controller CPLD special purpose pins.

See also TE0782 CPLD reference Wiki page.

Default PS MIO Mapping

Table 8: Zynq PS MIO mapping

Gigabit Ethernet

The TE0782 is equipped with two Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input for both PHYs is supplied from an on board 25MHz oscillator (U11), the 125MHz output clock of both PHYs are connected to Zynq's PL bank 35.

ETH1 PHY connection:

Table 9: General overview of the Gigabit Ethernet1 PHY signals

ETH2 PHY connection:

Table 10: General overview of the Gigabit Ethernet2 PHY signals

USB Interface

The TE0782 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).

USB0 PHY connection:

Table 11: General overview of the USB0 PHY signals

USB1 PHY connection:

Table 12: General overview of the USB1 PHY signals

I2C Interface

The on-board I²C components are connected to bank 35 pins L15 (I2C_SDA) and L14 (I2C_SCL).

I²C addresses for on-board components:

Table 13: Address table of the I²C bus slave devices

Pin Definitions

Pins with names ending with _VRN and _VRP are connected to Zynq PL HP bank special purpose pins VRN/VRP and can be routed to DCI calibration resistors on the baseboard. Otherwise they are usable as general purpose I/Os.

Bank 35 has 100 ohm DCI calibration resistors installed, it is also possible to "borrow" the DCI calibration from bank 35 for banks 34 and 33. For more detailed information about the DCI check Xilinx documentation.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U14) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0782 CPLD reference Wiki page.

eMMC Flash Memory

eMMC Flash memory device (U15) is connected to the Zynq PS MIO bank 500 pins MIO10..MIO15. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

DDR3L Memory

By default TE0782-02 module has two 16-bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) chips (U10, U19) arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM.

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash memory for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 (U38) with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet PHYs

On-board Gigabit Ethernet PHYs (U18, U20) are provided by Marvell Alaska 88E1512. The Ethernet PHYs' RGMII interfaces are connected to the Zynq's PS MIO bank 501 and to PL bank 9. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of both PHYs is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB ULPI PHYs

Hi-speed USB ULPI PHYs (U4. U8) are provided with USB3320 from Microchip. The ULPI interfaces are connected to the Zynq PS USB0 and USB1 via MIO28..51, bank 501 (see also section USB interface). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U7).

MAC Address EEPROMs

Two Microchip 24AA025E48 serial EEPROMs (U22, U24) contain globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The devices are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROMS areaccessible over I²C bus (see also section I²C interface).

Configuration EEPROM

The TE0782 board contains one EEPROM (U26) for configuration and general user purposes. The EEPROMs is provided by Microchip 24LC128-I/ST with 128 KBit memory density, the EEPROM is areaccessible over I²C bus (see also section I²C interface).

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U2) chip on-board. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator (U3) is connected to the pin IN3 and is used to generate the output clocks. The output voltage of the oscillator is provided by the 1.8V power rail, thus making output frequency available as soon as 1.8V is present. All 4 of the Si5338 clock outputs are connected to the MGT banks of the Zynq device. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

Table 14: General overview of the on-board quad clock generator I/O signals

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table 15: Reference clock signals

On-board LEDs

Table 16: On-board LEDs

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 4A for system startup is recommended.

Power Consumption

Table 17: Power consumption

 * TBD - To Be Determined soon with reference design setup.

Power Distribution Dependencies

The Trenz TE0782 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

The power supply voltage 'C3.3V' of System Controller CPLD of the SoM have to be externally supplied with 3.3V nominal.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0782 module.

Power-On Sequence

Power-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

Power Rails

Table 18: Module power rails

Bank Voltages

Table 19: Module I/O bank voltages

See Xilinx Zynq-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

The TE0782 SoM has three 160-pin double-row ASP-122952-01  Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 20: Module absolute maximum ratings

Recommended Operating Conditions

Table 21: Recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 85 mm × 85 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 5 mm

• PCB thickness: 1.7 mm

All dimensions are shown in millimeters.

Revision History

Hardware Revision History

Table 22: Hardware revision history table

Document Change History

<!--
Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

Disclaimer