Page History
...
- Intel MAX 10 10M08 FPGA SoC, U1
- 8 Mbyte SDRAM 166MHz, U2
- 8 Mbyte SPI QSPI Flash memory, U5
- ST Microelectronics LIS3DH 3-axis accelerometer, U4
- FTDI USB2 to JTAG/UART adapter, U3
- Configuration EEPROM for FTDI chip, U9
- 12.0000 MHz oscillator, U7
- 8x red user LEDs, D2 ... D9
- Red LED (Conf. DONE), D10
- Green LED (indicating supply voltage), D1
- Push button (user), S2
- Push button (reset), S1
- Micro USB2 B socket (receptacle), J9
- 1x14 pin header (2.54mm pitch), J2
- 1x6 pin header (2.54mm pitch), J4
- 2x6 Pmod connector, J6
- 3-pin header (2.54mm pitch), J3
- 1x14 pin header (2.54mm pitch), J1
...
Storage device name | Content | Notes |
|---|---|---|
Quad SPI Flash, U5 | DEMO Design | - |
| I2C Configuration EEPROM, U9 | Programmed | - |
...
| Bank | I/O's Count | Connected to | Notes |
|---|---|---|---|
| 2 | 4 | 1x14 pin header, J1 | user GPIO's |
| 8 | Pmod connector, J6 | user GPIO's | |
| 1 | clock oscillator, U7 | 12.0000 MHz reference clock input | |
| 1 | optional clock oscillator, U6 | oscillator not fitted, footprints available for Microchip MEMS oscillator | |
| 5 | 9 | 1x14 pin header, J2 | 2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6 |
| 6 | 18 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface |
| 3 | 22 | 8 MByte SDRAM 166MHz, U2 | 16bit SDRAM memory interface |
| 6 | LIS3DH 3-axis accelerometer, U4 | 4 I/O's for SPI interface, 2 interrupt lines | |
| 1A | 8 | 1x14 pin headers J1 | 7 analog inputs or GPIO's, 1 pin analog reference voltage input |
| 2 | pin headers J1 | 1 analog inputs or GPIO, 1 dedicated analog input | |
| 1B | 5 | pin header J4 | 4 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND |
| 8 | 8 | LEDs D2 ... D9 | Red user LEDs |
| 6 | SPI Flash memory, U5 | 4 6 pins Quad SPI interface, 2 control linesof them pulled up as configuration pins during initialization | |
| 6 | FTDI FT2232H JTAG/UART Adapter, U3 | 6 pins configurable as GPIO/UART or other serial interfaces | |
| 1 | Red LED, D10 | Configuration DONE Led (ON when configuration in progress, OFF when configuration is done) | |
| 1 | User button S2 | user configurable | |
| 1 | Reset button S1 and pin J2-10 | low active reset line for FPGA reconfiguration |
...
| JTAG Signal | Pin on Header J4 | Note |
|---|---|---|
| TCK | 3 | - |
| TDI | 5 | - |
| TDO | 4 | - |
| TMS | 6 | - |
| JTAGEN | 2 | -leave floating when use JTAG interface |
Table 4: optional JTAG pin header
...
| Serial Memory U5 Pin | Signal Schematic Name | Connected to | Notes | ||
|---|---|---|---|---|---|
| Pin 21, DATA1CS | ASF_DATA0CS | FPGA bank 18, pin H2B3 | Data outchip select | ||
| Pin 56, DATA0CLK | ASF_ASDOCLK | FPGA bank 1, pin C1A3 | Data inclock | ||
| Pin 15, nCSSI/IO0 | ASF_NCSDI | FPGA bank 1, pin D2A2 | data in / outchip select | ||
| Pin 67, DCLKHOLD/IO3 | NSTATUSAS_DCLK | FPGA bank 1, pin C4 | data in / out | ||
| Pin 3, WP/IO2 | DEVCLRN | FPGA bank 8, pin H1 | clock | B9 | data in / out |
| Pin 2, SO/IO1 | F_DO | FPGA bank 8, pin B2 | data in / outPin 6, DCLK |
Table 5: Serial configuration Quad SPI Flash memory interface connections
SDRAM
The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2. This SDRAM chip is connected to the FPGA bank 7 and 8 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
...
Overview
Content Tools