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Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:
| JTAG Signal | Pin on Header J4 | Note |
|---|---|---|
| TCK | 3 | - |
| TDI | 5 | - |
| TDO | 4 | - |
| TMS | 6 | - |
| JTAGEN | 2 | leave floating when use JTAG interface, otherwise signals on FPGA are GPIOs |
Table 4: optional JTAG pin header
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