Page History

<!--
Template Revision 1.68
(HTML comments will be not displayed in the document, no need to remove them. For Template/Skeleton changes, increase Template Revision number. So we can check faster, if the TRM style is up to date).
-->

<!--
General Notes:
If some section is CPLD firmware dependent, make a note and if available link to the CPLD firmware description. It's in the TE shop download area in the corresponding module -> revision -> firmware folder.
-->

<!--
General Notes:
Designate all graphics and pictures with a number and a description. For example "Figure 1: TE07xx-xx Block Diagram" or "Table 1: Initial delivery state". "Figure x" and "Table x" have to be formatted to bold.  
-->

<!--
Link to the base folder of the module (remove de/ or en/ from the URL): for example:
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0703/
  -->

Overview

The Trenz Electronic TEI0001 MAX1000 is a low cost small-sized FPGA module integrating a Intel MAX 10 FPGA SoC, 8 MByte serial memory for user application, 8 MByte SDRAM and a 3-axis accelerometer.

<!--
Use short link the Wiki Ressource page: for example:
http://trenz.org/te0720-info
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects
 -->

Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation.

Key Features

• Intel MAX 10 10M08 FPGA SoC

• 8 MByte SDRAM

• 8 MByte QSPI Flash memory

• ST Microelectronics LIS3DH 3-axis accelerometer
  
• JTAG and UART over Micro USB2 connector
• 1x6 pin header for JTAG access to FPGA SoC
• 1x PMOD header providing 8 GPIOs

• 2x 14-pin headers (2,54 mm pitch) providing 22 GPIOs with 7 analog inputs as alternative function

• 1x 3-pin header providing 2 analog inputs or 1 GPIO

• 8x user LEDs

• 1x user push button
• 5.0V single power supply with on-board voltage regulators
• Size: 61.5 x 25 mm
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

1. Intel MAX 10 10M08 FPGA SoC, U1
2. 8 Mbyte SDRAM 166MHz, U2
3. 8 Mbyte QSPI Flash memory, U5
4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
5. FTDI USB2 to JTAG/UART adapter, U3
6. Configuration EEPROM for FTDI chip, U9
7. 12.0000 MHz oscillator, U7
8. 8x red user LEDs, D2 ... D9
9. Red LED (Conf. DONE), D10
10. Green LED (indicating supply voltage), D1
11. Push button (user), S2
12. Push button (reset), S1
13. Micro USB2 B socket (receptacle), J9
14. 1x14 pin header (2.54mm pitch), J2
15. 1x6 pin header (2.54mm pitch), J4
16. 2x6 Pmod connector, J6
17. 3-pin header (2.54mm pitch), J3
18. 1x14 pin header (2.54mm pitch), J1

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:

Table 4: optional JTAG pin header

On-board Peripherals

Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Winbond W74M64FVSSIQ with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via SPI interface.

Table 5: Quad SPI Flash memory interface

SDRAM

The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

Table 6: 16bit SDRAM memory interface

FTDI FT2232H Chip

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

Table 7: FTDI chip interfaces and pins

3-Axis Accelerometer

On the TEI0001 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

Table 8: 3-axis accelerometer interfaces and pins

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Table 9: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

Table 10: LEDs of the module

Push Buttons

The FPGA module is equipped with two push buttons S1 and S2:

Table 11: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEI0001 module needs one single power supply of 5.0V nominal.

There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:

Power Consumption

Table 12: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Power Rails

Table 13: Connector power pin description

Bank Voltages

Table 14: FPGA SoC VCCO bank voltages

Technical Specifications

Absolute Maximum Ratings

Table 15: Absolute maximum ratings

Recommended Operating Conditions

Table 16: Recommended operating conditions

Physical Dimensions

• Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

• PCB thickness: ca. 1.65mm

• Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.

Revision History

Hardware Revision History

Table 17: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Document Change History

v.17

Table 18: Document change history

Disclaimer