Page History
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- JTAG routing
- Boot Mode settings
- PUDC
- LED
Firmware Revision and supported PCB Revision
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| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| C_TCK | in | 30 | 3.3VIN | JTAG B2B |
| C_TDI | in | 32 | 3.3VIN | JTAG B2B |
| C_TDO | out | 1 | 3.3VIN | JTAG B2B |
| C_TMS | in | 29 | 3.3VIN | JTAG B2B |
| EN1 | in | 27 | 3.3VIN | Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback |
| User_LED | out | 4 | 3.3VIN | user defined or status, see LED description |
| N.C. | 5 | 3.3VIN | / currently_not_used | |
| JTAGEN | in | 26 | 3.3VIN | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
| MODE | in | 25 | 3.3VIN | Boot Mode for Zynq/ZynqMP Devices (Flash or SD) |
| MODE0 | out | 12 | 1.8V | ZynqMP Boot Mode Pin 0 |
| MODE1 | out | 13 | 1.8V | ZynqMP Boot Mode Pin 1 |
| MODE2 | out | 14 | 1.8V | ZynqMP Boot Mode Pin 2 |
| MODE3 | out | 16 | 1.8V | ZynqMP Boot Mode Pin 3 |
| NOSEQ | inout | 23 | 3.3VIN | usage CPLD Variant depends |
| PGOOD | out | 28 | 3.3VIN | Module Power Good (only Feedback from EN1). |
| PUDC_B | out | 17 | 1.8V | PUD_C → external pullup / currently_not_used |
| TCK | out | 9 | 1.8V | JTAG ZynqMP |
| TDI | out | 8 | 1.8V | JTAG ZynqMP |
| TDO | in | 10 | 1.8V | JTAG ZynqMP |
| TMS | out | 11 | 1.8V | JTAG ZynqMP |
| X0 | in | 20 | VCCO_65 | FPGA IO (FPGA Pin B1) / Enable User LED (negative) |
| X1 | in | 21 | VCCO_65 | FPGA IO (FPGA Pin C1)/ Connect to User LED |
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| Note |
|---|
NOSEQ*: Please check the carrier board documentation, before using the SD/QSPI/JTAG firmware variant on TE0820TE0821. In the most cases special carrier CPLD firmware is needed. |
PUDC
const. 1 → The I/Os will be 3-stated after power-on when PUDC is High.
Power
PGOOD is EN1. There is no additional power management controlled by CPLD.
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