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CPLD Device: LCMX02-256HC
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Name | Direction | Pin | Description |
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3.3V / PG_SENSE | in | 25 | Power Sense |
DONE | in | 28 | FPGA Done Pin |
EN1 | in | 11 | Enable Pin From B2B |
F_TCK | out | 17 | JTAG from/to FPGA |
F_TDI | out | 23 | JTAG from/to FPGA |
F_TDO | in | 9 | JTAG from/to FPGA |
F_TMS | out | 10 | JTAG from/to FPGA |
FPGA_IO1 | in | 21 | FPGA Pin |
FPGA_IO2 | 20 | / currently_not_used | |
FTDI_RESET_N | out | 5 | USB FTDI Reset |
JTAGEN | in | 26 | Switch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA) |
MODE | in | 13 | / currently_not_used |
NOSEQ | inout | 14 | / currently_not_used |
PG_DDR_PWR | in | 4 | Power Good from DDR |
PGOOD | out | 12 | Power Good to B2B |
PROG_B | out | 27 | FPGA PROG_B |
RESIN | in | 16 | Reset Pin From B2B |
SYSLED1 | out | 8 | LED (Green) |
TCK | in | 30 | JTAG from/to B2B |
TDI | in | 32 | JTAG from/to B2B |
TDO | out | 1 | JTAG from/to B2B |
TMS | in | 29 | JTAG from/to B2B |
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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).
Power Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD).
PROG_B is on if Power Good is high.
PROG_B is on if Power Good is high.
LED | Description |
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SYSLED1(Green) | ON when RESIN=0, else FGPIO1 when DONE=1 else Blinking |
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||||
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| REV01 | REV01 |
| Work in progressRevision 01 finished | ||||||||||||||||||||||||
2017-03-06 | v.1 | REV01 | REV01 |
| Initial release | ||||||||||||||||||||||||
All |
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