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Template Revision 2.1

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

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Overview

CPLD Device with designator U5: LCMX02-1200HC. CC703S is minimum startup design.

Feature Summary

JTAG
UART
Power
Boot Mode
Reset
SD
LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD Name	Direction	Pin	Pullup/Down	Bank Power	Description
ACBUS4		141			/ currently_not_used
ACBUS5		140			/ currently_not_used
ADBUS4		143			/ currently_not_used
ADBUS7		142			/ currently_not_used
BCBUS0		122			/ currently_not_used
BCBUS1		121			/ currently_not_used
BDBUS2		133			/ currently_not_used
BDBUS3		132			/ currently_not_used
BDBUS4		128			/ currently_not_used
BDBUS5		127			/ currently_not_used
BDBUS6		126			/ currently_not_used
BDBUS7		125			/ currently_not_used
CM0	in	76	UP	3.3V	DIP-S2 / used as JTAG Selection/ If CM0 set to high → Access to CPLD of module otherwise access to FPGA of module.
CM1	in	75	UP	3.3V	DIP-S1

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/ Used to change PGOOD pin state/ If CM1 set to high → PGOOD = '1' otherwise '0'/~~PIN forwarding (To work with PCB REV02,03,03)~~
E_SD_CMD		110			/ currently_not_used
E_SD_DAT0		106			/ currently_not_used
E_SD_DAT1		107			/ currently_not_used
E_SD_DAT2		112			/ currently_not_used
E_SD_DAT3		111			/ currently_not_used
E_SD_SCLK		109			/ currently_not_used
EN1	out	81	UP	3.3V	B2B Power Enable
FL_0	inout	28			LED (D3-red) / Status / not connected on REV02,REV03,REV04
FL_1	inout	27			LED (D4-green) / Status / not connected on REV02,REV03,REV04
FT_B_RX	out	138	NONE	3.3V	FTDI UART
FT_B_TX / BDBUS0	in	139	UP	3.3V	FTDI UART
JTAGEN		120			Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3
M_TCK	in	131	NONE	3.3V	JTAG from/to FTDI
M_TDI	in	136	NONE	3.3V	JTAG from/to FTDI
M_TDO	out	137	NONE	3.3V	JTAG from/to FTDI
M_TMS	in	130	NONE	3.3V	JTAG from/to FTDI
MIO0	in	94	UP	3.3V	DIP-S4 and B2B Pin / used as Boot Mode
MIO10		98			/ currently_not_used
MIO11		97			/ currently_not_used
MIO12	in	100	NONE	3.3V	B2B-Module UART2 TX
MIO13	out	99	NONE	3.3V	B2B-Module UART2 RX
MIO14	out	105	NONE	3.3V	B2B-Module UART RX
MIO15	in	95	NONE	3.3V	B2B-Module UART TX
MIO9	out	96	NONE	3.3V	SD_CD / not usable as SD_CD on REV02,REV03,REV04
MODE	out	83	NONE	3.3V	Boot Mode Pin. Switch Boot mode of Module (depends on module)
NOSEQ	inout	78	UP	3.3V	Add Pullup only / currently_not_used
PGOOD	inout	82	UP	3.3V	Add Pullup used for Status / currently_not_used
PHY_LED1	out	86	DOWN	3.3V	Status / currently_not_used
PHY_LED1R	out	92	NONE	3.3V	Status / currently_not_used
PHY_LED2	out	85	NONE	3.3V	Status / currently_not_used
PHY_LED2R	out	91	NONE	3.3V	Status / currently_not_used
PROGMODE	out	104	UP	3.3V	Enable B2B Module JTAG access to CPLD for Firmware update
RESIN	out	119	NONE	3.3V	Module Reset Pin on B2B connector
S1	in	114	UP	3.3V	Push Button / Used as module Reset
SD_CD	in	93	UP	3.3V	Forward to MIO 9 / not connected on REV02,REV03,REV04
SD_SEL	out	113	NONE	3.3V	set to GND / currently_not_used
TCK_B	out	1	NONE	3.3V	JTAG from/to Module
TDI_B	out	3	NONE	3.3V	JTAG from/to Module
TDO_B / C_TDO	in	2	UP	3.3V	JTAG from/to Module
TMS_B	out	4	NONE	3.3V	JTAG from/to Module
ULED1 / LED1	out	117	NONE	3.3V	LED (D1-red) / UART Monitoring
ULED2 / LED2	out	115	NONE	3.3V	LED /D2-green) / UART Monitoring
USB_OC		73			/ currently_not_used
X0		39			/ currently_not_used
X1		38			/ currently_not_used
X10		49			/ currently_not_used
X11		50			/ currently_not_used
X12		52			/ currently_not_used
X13		54			/ currently_not_used
X14		55			/ currently_not_used
X15		56			/ currently_not_used
X16	in	59	UP	3.3V	UART2 on VG connector J2
X17	out	60	NONE	3.3V	UART2 on VG connector J2
X2		40			/ currently_not_used
X3		41			/ currently_not_used
X4		42			/ currently_not_used
X5		43			/ currently_not_used
X6		44			/ currently_not_used
X7		45			/ currently_not_used
X8		47			/ currently_not_used
X9		48			/ currently_not_used

Functional Description

JTAG

JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module).

TE0703 CPLD can be select with JTAGEN (DIP-S2-3).

Module FPGA/CPLD access can be switched

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CM0 is pulled up with CPLD.

If used SoM on the carrier board is TE0715, it must be programmed a different jed file to arrange CPLD JTAG pins correctly. This module is an exception. For this purpose it is defined a generic parameter in vhdl code to switch JTAG pins differently as other SoM modules. There are two jed files. TE0715 CPLD with default jed file can not be programmed. But optional jed file exists for programming CPLD of TE0715 module. In both cases the following table is valid:

S2-2	S2-3	PROGMODE (S2-2)	JTAGEN (S2-3)	Description
OFF	OFF	1	1	Access to TE0703 CPLD
OFF	ON	1	0	Access to CPLD of B2B Module
ON	OFF	0	1	Access to TE0703 CPLD
ON	ON	0	0	Access to FPGA of B2B Module

Note: LED1,2,3,4 are on and PHY LEDs blink slow, if S2-2 is set to OFF.

Power

EN1 is set to one.

NOSEQ and PGOOD pulled up to VDD. NOSEQ pin is either high impedance or is used as JTAG pin to program CPLD of TE0715 module. PGOOD pin can be set or reset by user. If CM0 or CM1 set to high (S2-2 or S2-1 OFF) , PGOOD will be set to high otherwise PGOOD is set to low.

Reset

RESIN is driven by S1 (Push Button). Button is debounced.

Boot Mode

MODE Pin is sourced by

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MIO0. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP.

If CPLD of module is programmed with default jed file (QSPI/JTAG/SD), PGOOD pin will be used as second select pin for boot mode selection. In this case the following table can be considered:

S2-1	S2-4	PGOOD	MIO0	Description
ON	ON	0	0	JTAG boot mode
OFF	ON	1	0	SD Card boot mode
OFF	OFF	1	1	QSPI boot mode

But if MODE pin is selected as single boot mode selection pin (other optional jed files), the following table is valid:

S2-4

MIO0

Description

ON

0

def. SD-CARD Boot (for Zynq Modules), PHY LEDs glow orange

SD Card boot mode

OFF

1

def. QSPI-Flash, PHY LEDs glow green

QSPI boot mode

UART

Primary UART:

MIO14 is driven by BDBUS0 (FTDI RX).

BDBUS1 (FTDI TX) is driven by MIO15 .

Secondary UART:

MIO13 is driven by X16.

X17 is driven by MIO12.

SD

SD selection is set to GND (SD Card slot).

MIO9 is switched to SD_CD and

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its status depends on SD_CD .

Note: PCB REV02,REV03,REV04 has no SD~~, set S2-1 to ON~~

LED

LED Priority is order of the description

LED	Prio 0: Power	Prio 1: Modul CPLD access*	Prio 2
LED1 (D1-red)	Blink, if Power Good is low	ON	FTDI UART RX
LED2 (D2-green)	Blink, if Power Good is low	ON	FTDI UART TX
LED3 (D3-red)	Blink, if Power Good is low	ON	User defined with B2B Pin JB2-99
LED4 (D4-green)	Blink, if Power Good is low	ON	User defined with B2B Pin JB2-90
PHY LEDs (green/orange)	Blink orange, if Power Good is low	Blink Green and orange	Green: Boot Mode set to QSPI, Orange: Boot Mode set to SD

*Attention: LED1,2,3,4 are on, if S2-2 is set to OFF. If S2-3 is OFF, TE0703 is in chain!

Appx. A: Change History and Legal Notices

Revision Changes

REV02 to REV03
- Oscillator frequency is changed from 12.09 MHz to 24.18 MHZ.
- Access to CPLD of TE0715 with a generic parameter added.
- MODE, EN1 are pulled up.
- PGOOD used as second boot mode selector pin. PGOOD and MODE are boot mode selector pins.
REV02 to older REV01
- Enable CPLD access to module CPLD over DIP
- Add MIO0, SD_SEL, SD_CD, NOSEQ, PGOOD, 2LEDs, PHY LEDs
- Debounce button
- More status LED functionality

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
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Page info

	modified-user
	modified-user

Working in process

2019-11-08

v.13

REV02

REV02*,REV03*,REV04*,REV05, REV06 *some IOs are not connected *SD_CD not available, set S2-1 to on

John Hartfiel

Typo
Note PCB REV06 support

2017-10-13

v.11

REV02

REV02*,REV03*,REV04*,REV05
*some IOs are not connected
*SD_CD not available, set S2-1 to on

John Hartfiel

REV 02 finished

2016-04-11

v.1

REV02

REV02*,REV03*,REV04*,REV05
*some unused IOs are not connected
*SD_CD not available, set S2-1 to on

John Hartfiel

Initial release

All

John Hartfiel

Appx. B: Legal Notices

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	IN:Legal Notices

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Trenz Electronic Documentation

Versions Compared

Old Version 13

New Version 14

Key

Table of contents

Overview

Feature Summary

Firmware Revision and supported PCB Revision

Product Specification

Port Description

Functional Description

JTAG

Power

Reset

Boot Mode

UART

SD

LED

Appx. A: Change History and Legal Notices

Revision Changes

Document Change History

Appx. B: Legal Notices

Table of contents