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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
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Table of contents
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Overview
CPLD Device with designator U5: LCMX02-1200HC. CC703S is minimum startup design.
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Module FPGA/CPLD access can be switched with PROGMODE which is driven by CMD0 (DIP-S2-2).CMD0 is pulled up with CPLD.
| S2-2 | S2-3 | PROGMODE | JTAGEN | Description |
|---|---|---|---|---|
| OFF | OFF | 1 | 1 | access to TE0703 CPLD |
| OFF | ON | 1 | 0 | access to CPLD of B2B Module |
| ON | OFF | 0 | 1 | access to TE0703 CPLD |
| ON | ON | 0 | 0 | access to FPGA of B2B Module |
Power
EN1 is set to one.
Reset
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MODE Pin is sourced by MIO. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP.
| S2-4 | MIO0 | Description |
|---|---|---|
| ON | 0 | def. SD-CARD Boot(for Zynq Modules) |
| OFF | 1 | def. QSPI-Flash |
UART
Primary UART:
MIO14 is driven by BDBUS0 (FTDI RX).
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X17 is driven by MIO12.
LED
| LED | Description |
|---|---|
| LED1 (D1-red) | ON, if CMD0=1 else not FTDI_RXD |
| LED2 (D2-green) | ON, if CMD0=1 else not FTDI_TXD |
Appx. A: Change History and Legal Notices
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV01 | REV02*,REV03*,REV04*,REV05 |
| Work in progress | ||||||||||||||||||||||
| 2016-04-11 | v.1 | --- | REV02*,REV03*,REV04*,REV05 *some unused IOs are not connected |
| Initial release | ||||||||||||||||||||||
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Legal Notices
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Overview
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