Page History
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CPLD Device: LCMX02-256HC
Feature Summary
JTAG routing
Pinheader routing
Firmware Revision and supported PCB Revision
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Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Description |
|---|---|---|---|
| A | in | 8 | XMOD Pin Header / |
| ACBUS4 | 27 | FTDI / currently_not_used | |
| ACBUS5 | 28 | FTDI / currently_not_used | |
| ADBUS4 |
| 5 | FTDI / currently_not_used | ||
| B | out | 12 | XMOD Pin Header / |
| BDBUS2 | in | 21 | FTDI / currently_not_used |
| BDBUS3 | out | 20 | FTDI / currently_not_used |
| C | out | 9 | XMOD Pin Header / |
| D | in | 11 | XMOD Pin Header / |
| E | in | 14 | XMOD Pin Header / |
| F | out | 13 | XMOD Pin Header / |
| FT_B_RX / BDBUS1 | out | 25 | FTDI |
| FT_B_TX / BDBUS0 | in | 23 | FTDI |
| G | in | 17 | XMOD Pin Header / Pushbutton S1 |
| H | out | 16 | XMOD Pin Header / |
| JTAGEN | in | 26 | Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-1 |
| TCK / ADBUS0 | in | 30 | FTDI |
| TDI / ADBUS1 | in | 32 | FTDI |
| TDO / ADBUS2 | out | 1 | FTDI |
| TMS / ADBUS3 | in | 29 | FTDI |
| ULED | out | 10 | LED D4 (RED) |
| XCLK | in | 4 | 12 MHz OSCI Ref CLK / currently_not_used |
Functional Description
JTAG
Power
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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).
UART
UART is routed through the CPLD.
| Output | Input |
|---|---|
| B | BDBUS0 |
| BDBUS1 | A |
LED
ULED is E xor not G
Appx. A: Change History and Legal Notices
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| REV01 | REV02 |
| Work in progress | ||||||||||||||||||||||
| 2016-04-11 | v.1 | --- | REV02 |
| Initial release | ||||||||||||||||||||||
| All |
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Overview
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