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Template Revision 2.1

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

  • Change List 2.0 to 2.1
    • Fix problem with pdf export and side scroll bar
  • Change List 1.9.1 to 2.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator


Overview

CPLD Device with designator U5: LCMX02-1200HC. CC703S is minimum startup design.

Feature Summary

  • JTAG
  • UART
  • Power
  • Boot Mode
  • Reset
  • SD
  • LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
ACBUS4
141

 / currently_not_used
ACBUS5
140

 / currently_not_used
ADBUS4
143

 / currently_not_used
ADBUS7
142

 / currently_not_used
BCBUS0
122

 / currently_not_used
BCBUS1
121

 / currently_not_used
BDBUS2
133

 / currently_not_used
BDBUS3
132

 / currently_not_used
BDBUS4
128

 / currently_not_used
BDBUS5
127

 / currently_not_used
BDBUS6
126

 / currently_not_used
BDBUS7
125

 / currently_not_used
CM0in76UP3.3VDIP-S2 / used as JTAG Selection/ If CM0 set to high → Access to CPLD of module otherwise access to FPGA of module.
CM1in75UP3.3VDIP-S1 / Used to change PGOOD pin state/ If CM1 set to high → PGOOD = '1' otherwise '0'/PIN forwarding (To work with PCB REV02,03,03)
E_SD_CMD
110

 / currently_not_used
E_SD_DAT0
106

 / currently_not_used
E_SD_DAT1
107

 / currently_not_used
E_SD_DAT2
112

 / currently_not_used
E_SD_DAT3
111

 / currently_not_used
E_SD_SCLK

109



 / currently_not_used
EN1out81UP3.3VB2B Power Enable
FL_0inout28

 LED (D3-red) / Status  / not connected on REV02,REV03,REV04
FL_1inout27

LED (D4-green) / Status / not connected on REV02,REV03,REV04
FT_B_RXout138NONE3.3VFTDI UART
FT_B_TX / BDBUS0in139UP3.3VFTDI UART
JTAGEN
120

Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-3
M_TCKin131NONE3.3VJTAG from/to FTDI
M_TDIin136NONE3.3VJTAG from/to FTDI
M_TDOout137NONE3.3VJTAG from/to FTDI
M_TMSin130NONE3.3VJTAG from/to FTDI
MIO0in94UP3.3VDIP-S4 and B2B Pin / used as Boot Mode
MIO10
98

 / currently_not_used
MIO11
97

 / currently_not_used
MIO12in100NONE3.3VB2B-Module UART2 TX
MIO13out99NONE3.3VB2B-Module UART2 RX
MIO14out105NONE3.3VB2B-Module UART RX
MIO15in95NONE3.3VB2B-Module UART TX
MIO9 out96NONE3.3V SD_CD / not usable as SD_CD on REV02,REV03,REV04
MODEout83NONE3.3VBoot Mode Pin. Switch Boot mode of Module (depends on module)
NOSEQ inout78UP3.3VAdd Pullup only / currently_not_used
PGOOD inout82UP3.3VAdd Pullup used for Status / currently_not_used
PHY_LED1 out86DOWN3.3V Status / currently_not_used
PHY_LED1R out92NONE3.3V Status / currently_not_used
PHY_LED2 out85NONE3.3V Status /  currently_not_used
PHY_LED2R out91NONE3.3V Status / currently_not_used
PROGMODEout104UP3.3VEnable B2B Module JTAG access to CPLD for Firmware update
RESINout119NONE3.3VModule Reset Pin on B2B connector
S1in114UP3.3VPush Button / Used as module Reset
SD_CD in93UP3.3VForward to MIO 9 / not connected on REV02,REV03,REV04
SD_SEL out113NONE3.3Vset to GND / currently_not_used
TCK_Bout1NONE3.3VJTAG from/to Module
TDI_Bout3NONE3.3VJTAG from/to Module
TDO_B / C_TDOin2UP3.3VJTAG from/to Module
TMS_Bout4NONE3.3VJTAG from/to Module
ULED1 / LED1out117NONE3.3VLED (D1-red) / UART Monitoring
ULED2 / LED2out115NONE3.3VLED /D2-green) / UART Monitoring
USB_OC
73

 / currently_not_used
X0
39

 / currently_not_used
X1
38

 / currently_not_used
X10
49

 / currently_not_used
X11
50

 / currently_not_used
X12
52

 / currently_not_used
X13
54

 / currently_not_used
X14
55

 / currently_not_used
X15
56

 / currently_not_used
X16in59UP3.3VUART2 on VG connector J2
X17out60NONE3.3VUART2 on VG connector J2
X2
40

 / currently_not_used
X3
41

 / currently_not_used
X4
42

 / currently_not_used
X5
43

 / currently_not_used
X6
44

 / currently_not_used
X7
45

 / currently_not_used
X8
47

 / currently_not_used
X9
48

 / currently_not_used

Functional Description

JTAG

JTAG signals routed directly through the CPLD to module in B2B connector. Access between CPLD and module can be multiplexed via JTAGEN (logical one for CPLD, logical zero for module). TE0703 CPLD can be select selected with JTAGEN (DIP-S2-3). Module FPGA/CPLD access can be switched with PROGMODE which is driven by CM0 (DIP-S2-2).CM0 is pulled up with CPLD.

If used SoM on the carrier board is TE0715, it CPLD of TE0703  must be programmed a different jed file to arrange CPLD JTAG pins correctly. This module is an exception.  For this purpose it is defined a generic parameter in vhdl code to switch JTAG pins differently as other SoM modules. There are two jed files. CPLD of TE0715 CPLD module with default jed file for CPLD of carrier board TE0703 can not be programmed. But optional jed file exists for programming CPLD of TE0715 modulethis purpose. In both cases default or optional jed file the following table is valid:

S2-2S2-3PROGMODE (S2-2)JTAGEN (S2-3)Description
OFFOFF11Access to TE0703 CPLD
OFFON10Access to CPLD of B2B Module
ONOFF01Access to TE0703 CPLD
ONON00Access to FPGA of B2B Module

Note: LED1,2,3,4 are on and PHY LEDs blink slow, if S2-2 is set to OFF.

Power

EN1 is set to one.

NOSEQ and PGOOD pulled up to VDD. NOSEQ pin is either high impedance or is used as JTAG pin to program CPLD of TE0715 module. PGOOD pin can be set or reset by user. If CM0 or CM1 set to high (S2-2 or S2-1 OFF) , PGOOD will be set to high otherwise PGOOD is set to low.

Reset

RESIN is driven by S1 (Push Button). Button is debounced.

Boot Mode

MODE Pin is sourced by MIO0. MIO0 connected DIP S2-4 and B2B connector. MIO is pulled up with CPLD and can be set to GND via DIP. If CPLD of module is programmed with default jed file (QSPI/JTAG/SD), PGOOD pin will be used as second select pin for boot mode selection. In this case the following table can be considered:  

S2-1S2-4PGOODMIO0Description
ONON00JTAG boot mode
OFFON10SD Card boot mode, PHY LEDs glow orange
OFFOFF11QSPI
boot mode

But if MODE pin is selected as single boot mode selection pin (other optional jed files), the following table is valid:

S2-4MIO0Description
ON0

def. SD-CARD Boot (for Zynq Modules), PHY LEDs glow orange

SD Card boot mode		OFF1def. QSPI-Flash, PHY LEDs glow greenQSPI boot mode

UART

Primary UART:

MIO14 is driven by BDBUS0 (FTDI RX).

BDBUS1 (FTDI TX) is driven by MIO15 .

Secondary UART:

MIO13 is driven by X16.

X17 is driven by MIO12.

SD

SD selection is set to GND (SD Card slot).

MIO9 is switched to SD_CD and its status depends on SD_CD .

Note: PCB REV02,REV03,REV04 has no SD, set S2-1 to ON

LED

LED Priority is order of the description

LEDPrio 0: PowerPrio 1: Modul CPLD access*Prio 2
LED1 (D1-red)Blink, if Power Good is lowONFTDI UART RX
LED2 (D2-green)Blink, if Power Good is lowONFTDI UART TX
LED3 (D3-red)Blink, if Power Good is lowOFFONUser defined with B2B Pin JB2-99
LED4 (D4-green)Blink, if Power Good is lowOFFONUser defined with B2B Pin JB2-90
PHY LEDs (green/orange)Blink orange, if Power Good is lowBlink Green and orangeGreen: Boot Mode set  to QSPI, Orange: Boot Mode set to SD

*Attention: LED1,2,3,4 are on, if S2-2 is set to OFF. If S2-3 is OFF, TE0703 is in chain!

Appx. A: Change History and Legal Notices

Revision Changes

  • REV02 to REV03

    • Oscillator frequency is changed from 12.09 MHz to 24.18 MHZ.

    •  Access to CPLD of TE0715 with a generic parameter added.

    • MODE, EN1 are pulled up.

    • PGOOD used as second boot mode selector pin. PGOOD and MODE are boot mode selector pins.

  • REV02 to older REV01
    • Enable CPLD access to module CPLD over DIP
    • Add MIO0, SD_SEL, SD_CD, NOSEQ, PGOOD, 2LEDs, PHY LEDs
    • Debounce button
    • More status LED functionality

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
prefixv.
typeFlat

REV03

REV02*,REV03*,REV04*,REV05, REV06 *some IOs are not connected *SD_CD not available

Page info
modified-user
modified-user

  • Working in process
2019-11-08v.13REV02REV02*,REV03*,REV04*,REV05, REV06 *some IOs are not connected *SD_CD not available, set S2-1 to onJohn Hartfiel
  • Typo
  • Note PCB REV06 support

2017-10-13

v.11




REV02

REV02*,REV03*,REV04*,REV05
*some IOs are not connected
*SD_CD not available, set S2-1 to on

John Hartfiel

  • REV 02 finished
2016-04-11

v.1

REV02

REV02*,REV03*,REV04*,REV05
*some unused IOs are not connected
*SD_CD not available, set S2-1 to on

John Hartfiel

  • Initial release

All

John Hartfiel


Appx. B: Legal Notices

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IN:Legal Notices
IN:Legal Notices




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