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Old Version 8

changes.mady.by.user John Hartfiel

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New Version 9

changes.mady.by.user Oleksandr Kiyenko

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Key

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Used only for CPLD Firmwareupdate. Second chip in JTAG chain when switch S3:2 is ON.

RESET

NameDescription
SSD1_PERSTnSC_IO0
ETH_RSTSlow Reset from SC_IO0
USB0_RSTSlow Reset from SC_IO0
USBH_RSTSlow Reset from SC_IO0
PLL_RSTSlow Reset from SC_IO0

 

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LEDs

LEDValueDescription
XMOD1_ECounter Bit or  XMOD1_G 
LED1_1Anot PHY_LED1Yellow LED is PHY RX Indicator (with default PHY settings)
LED_2Anot PHY_LED0Green LED is PHY LINK Indicator (with default PHY settings)
LED_2B0Stub to use only green from dual Green/Orange LED
LED1DP_TX_HPDDisplayPort Hotplug Detection
LED2hub_rst_nUSB hub reset indicator
LED3SSD1_LEDLED output from M2 slot
LED4F1_SENSE 
SFP_LED10 
SFP_LED20 
SFP_LED30 
SFP_LED40 

UART

OutputInput
MIO42XMOD1_B
XMOD1_AMIO43

 

Display Port

OutputInput
DP_AUX_TXB66_T1
DP_AUX_DEnot B66_T2
B66_T3DP_AUX_RX
B67_T1DP_TX_HPD

SD

SD_EN is "0". Enable power for SD slot.

SFP

All Transmit for all SFP is enabled.

USB

USB Mode pins constant "11" (default boot mode).

SSD

SSD1_WAKE is "0".

Anchor
i2c_ram
i2c_ram
I2C RAM

I2C Baseaddress: 0x74. I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 100 MHz supported.

Write access

Register AddressNameDescription
0FAN CTRL

Enable FAN, Bit 0-2 Fan1 to Fan2, Default all 1

1FAN1
RPS
PWMFAN1 PWM (0%-100%, Default 30%)
2FAN2
RPS
PWMFAN2 PWM (0%-100%, Default 30%)
3FAN3
RPSDefault 30%

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PWMFAN3 PWM (0%-100%, Default 30%)

Read access

Register AddressNameDescription
0FAN CTRLFAN Control register
1FAN1 RPSFAN1 Revolutions per second
2FAN2 RPSFAN2 Revolutions per second
3FAN3 RPSFAN3 Revolutions per second

 

FANs

See I2C RAM.

PLL

PLL Selection pins constant "00".

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