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Table of Contents
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Trenz Electronic TE0711 is an industrial-grade FPGA module integrating a Xilinx Artix-7 FPGA, 32 MByte Quad SPI Flash memory for configuration and operation and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/O's are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic SoM's in 4 x 5 cm form factor follow the same mechanical design rules, thus they are interchangeable.
Block Diagram
Figure 1: TE0711-01 block diagram.
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- Artix-7 (15T to 100T) FPGA
- EN6347QI voltage Regulator 1.0V
- EN5311QI voltage Regulator 1.8V
- S25FL256S 32 MByte Quad SPI Flash memory
- Dual USB to UART/FIFO Bridge (FT2232H)
- TPS27082L load switch for 3.3V voltage level
- B2B connector JM1 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- B2B connector JM2 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- B2B connector JM3 (0,40 mm Razor Beam™ High Speed Hermaphroditic Terminal/Socket Strip (LSHM-150))
- System Controller CPLD (Lattice LCMXO2-256HC): 256 Macrocell CPLD
- SiT8008AI 100 MHz reference clock (connected to FPGA bank 14)
- SiT8008AI 12 MHz reference clock (connected to USB to UART/FIFO Bridge)
- EEPROM (configuration data for USB to UART/FIFO Bridge)
- TPS3805H33 voltage detector for generating "Power OK"-signal indicating successful power-on-sequencing
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Key Features
Industrial-grade Xilinx Artix-7 (15T to 100T) SoM (System on Module), supported by the free Xilinx Vivado WebPACK tool
Rugged for shock and high vibration
- FTDI FT2232HQ USB 2.0 High Speed to UART/FIFO
32 MByte QSPI Flash memory (with XiP support)
100 MHz MEMS oscillator
Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
178 FPGA I/Os (84 differential pairs) are available on board-to-board connectors
On-board high-efficiency DC-DC converters
4.0 A x 1.0 V power rail
1.0 A x 1.8 V power rail
1.0 A x 1.5 V power rail
System management and power sequencing
eFUSE bit-stream encryption
AES bit-stream encryption
User LED
Evenly-spread supply pins for good signal integrity
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Storage Component | Content | Notes |
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SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
EFUSE USER | Not programmed | - |
EFUSE Security | Not programmed | - |
Table 1: Initial TE0711 initial delivery state.
Signals, Interfaces and Pins
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Table 4: Pin-description of System Controller CPLD.
LEDs
On the SoM TE0710 there is a total of 3 LEDS available. Two LEDs are status LEDs, one can freely used in costumer designs. The user LED is routed to the FPGA by the net with the schematic-name 'USERLED'.
When the FPGA is not configured the status LEDs will flash continuously. Finally once FPGA configuration has completed the status LEDs can be used in the user's FPGA design.
LED's
The TE0711 SoM has total of 4 on-board LED's. LED's D1, D2 and D3 are connected to the Xilinx Artix-7 FPGA and can be freely used by user design. LED D4 is the System Controller CPLD status LED.
LED | Color | Connected to | LED | Color | Connected to pin | Description and Notes |
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D1 | redRed | SYSLED2 | User LED, active HIGH, connected to FPGA Pin A8 | |||
D2 | greenGreen | SYSLED4 | User LED, active HIGH, connected to FPGA Pin R17 | |||
D3 | greenGreen | SYSLED3 | User LED, active LOW, connected to FPGA Pin L15 | |||
D4 | greenGreen | SYSLED1 | System Controller status LED, connected to CPLD |
Table 5: Description of the on-board LEDsLED's.
Clocking
The TE0710 TE0711 is equipped with two MEMS oscillators to provide clock signals for two on-board Ethernet PHY's and DDR3 SDRAM.
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Reference oscillator clock for USB to UART/FIFO Bridge (FT2232H)
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12 MHz
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MEMS oscillator (SiT8008AI-73-XXS-
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100.000000E
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U8 SiT8008AI-73-XXS-100.000000E
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, U8) to provide 100 MHz clock signal for Xilinx Artix-7 FPGA pin P17.
On-board Peripherals
32 MByte
Table 6: Clocks overview
Onboard Peripherals
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Quad SPI Flash Memory
An SPI flash memory S25FL256S (U7) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data rate will be dependent on the bus width and clock frequency.
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The TE0711-01 SoM has on-board high-speed USB 2.0 High Speed to UART/FIFO IC FT2232HQ controller from FTDI. Channel A can only be used in simple UART mode, . Channel B can be used as UART , in FT245 FIFO mode, JTAG (MPSSE) or High Speed Serial mode or in high-speed serial modes.
All FT2232HQ -pins are controller is connected to the FPGA bank 14 with fixed 3.3V VCCIO and should be used with LVCMOS33 all signalling must meet the LVCMOS 3.3V I/O Standardstandard.
There is also a standard 256 Byte EEPROM is connected to the FT2232HQ-chip available to store custom configuration settings. EEPROM These settings can be changed using FTDI provided tools that can be downloaded from FTDI website. See FTDI website for more information.
Power and Power-On Sequence
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Power Input Pin | Voltage Range | Max Current |
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VIN | 3.3V to 5.5V | Typical 200mA, depending on customer design and connections. |
3.3VIN | 3.3V | Typical 50mA, depending on customer design and connections. |
Table 76: maximal current of power suppliesTypical power consumption.
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Vin VIN and Vin 3VIN3.3V can be connected to the same power source (3.3 V3V). |
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises).
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For highest efficiency of on board DC/-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets STAT_SC2 signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx Artix-7 datasheet DS181 (for Artix7) for additional information. User should also Also check related baseboard documentation when choosing baseboard design for TE0711-01 module.
A 3.3V supply is also needed and must be supplied from the user's PCB. An output 3.3V supply is available on some of the board connector pins (see section 'Power Rails'). The input 3.3VIN will be switched to the internal 3.3V voltage level after the FPGA 1.0V supply is stablehas stabilized. Than 3.3V supply will be available on the B2B connector pins.
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Voltages on B2B- Connectors | B2B JM1-Pin | B2B JM2-Pin | Direction | Note |
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VIN | 1, 3, 5 | 2, 4, 6, 8 | input | supply voltage |
3.3VIN | 13, 15 | - | input | supply voltage |
VCCIO15 | 9, 11 | - | input | high range bank voltage |
VCCIO34 | - | 1, 3 | input | high range bank voltage |
VCCIO35 | 7, 9 | input | high range bank voltage | |
3.3V | 14 | 10, 12, 91 | output | internal 3.3V voltage level |
1.8V | 39 | - | output | internal 1.8V voltage level |
Table 87: Power rails of SoM on B2B connectors.
Bank Voltages
Bank | Schematic Name | Voltage | Range |
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0 Config | 3.3V | 3.3V | - |
14 | 3.3V | 3.3V | - |
15 | VCCIO15 | user | HR: 1.2V to 3.3V |
16 | 1.8V | 1.8V | - |
34 | VCCIO34 | user | HR: 1.2V to 3.3V |
35 | VCCIO35 | user | HR: 1.2V to 3.3V |
Table 98: Range of FPGA's bank voltages.
See the Artix7 datasheet DS181 for the allowable voltage range.
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Module Variant | FPGA | FPGA Junction Temperature | Operating Temperature Range |
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TE0711-01-100-2C | XC7A100T-2CSG324C | 0°C to 85°C | commercial Commercial grade |
TE0711-01-35-2C | XC7A35T-2CSG324C | 0°C to 85°C | commercial Commercial grade |
TE0711-01-100-2I | XC7A100T-2CSG324I | -40°C to 100°C | industrial Industrial grade |
TE0711-01-35-2I | XC7A35T-2CSG324I | -40°C to 100°C | industrial Industrial grade |
Table 109: Differences between variants of Module TE0711-01
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Parameter | Min | Max | Units | Notes |
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VIN supply voltage | -0.3 | 7.0 | V | EN6347QI / EN5311QI data sheet |
3.3VIN supply voltage | -0.1 | 3.6 | V | - |
PL IO bank supply voltage for HR I/O Banks (VCCO) | -0.5 | 3.6 | V | - I |
I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - Voltage |
Voltage on module JTAG pins | -0.5 | VCCO_0+0.45 | V | VCCO_0 is 3.3V nominal. Storage |
Storage temperature | -55 | +125 | °C | - |
Table 1110: Absolute maximum ratings.
Recommended
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Operating Conditions
Parameter | Min | Max | Units | Notes | Reference Document |
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VIN supply voltage | 2.4 | 5.5 | V | - | EN5311QI data sheet 3 |
3.3VIN supply voltage | 3.135 | 3.465 | V | - | 3,3V ± 5% PL |
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | - | Xilinx datasheet DS181 |
I/O input voltage for HR I/O Banks | - 0.20 | VCCO + 0.2 | V | - | Xilinx datasheet DS181 |
Voltage on Module JTAG pins | 3.135 | 3.465 | V | - | 3,3V ± 5% |
Table 1211: Recommended operation operating conditions.
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Please check Xilinx datasheet (DS181) for complete list of absolute maximum and recommended operating ratings. |
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Industrial grade: -40°C to +85°C.
The module Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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All dimensions are shown in mmmillimeters.
Figure 3: Physical Dimensions of the TE0711-01 board.
Weight
20.6 g | Plain module |
8.8 g | Set of bolts and nuts |
Table 11: Module weight data.
Revision History
Hardware Revision History
Date | Revision | Notes | PCN | Documentation link |
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01 | First production release Current Hardware Revision | TE0711 |
Table 12: Hardware revisions.
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
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Date | Revision | Contributors | Description |
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2017-01-01 | Ali Naseri, Jan Kumann | TRM revision | |
2015-06-05 | 0.1 | initial version |
Disclaimer
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