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32 MByte Quad SPI Flash Memory
An On-board SPI flash memory S25FL256S (U7) is provided for used to store initial FPGA configuration file storage. After Besides FPGA configuration completes the , remaining free flash memory can be used for user application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum Maximum data rate will be dependent depends on the bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high, or the FPGA would not configure from FlashFPGA is unable to load its configuration from flash. This bit is always set to high by default at the manufacturing plant. |
System Controller
The system controller is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Low level at NRST_SC0 pin also resets the FPGA. This signal can be driven from the user’s PCB via the B2B connector pin JM2-18. Input EN_SC3 is also gated to FPGA Reset and should be open or pulled up for normal operation. EN_SC3 low turns off on board DC-DC converters and stops power-on sequencing.
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