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NameDirectionPinDescription
B64_T1          out20FPGA IO / Master RGPIO TX
B64_T2          in19FPGA IO / Master  RGPIO RX
B64_T3          in21FPGA IO / Master  RGPIO CLK
B65_T1          out22FPGA IO  / Slave RGPIO TX
B65_T2          in24FPGA IO / Slave RGPIO RX
B65_T3          in23FPGA IO / Slave RGPIO CLK
C_TCK           in131JTAG
C_TDI           in136JTAG
C_TDO1          out137JTAG
C_TMS           in130JTAG
DDR_EN/EN_DDR         out126Power control
DDR_PG           121Power control / currently_not_used
DONE            in4FPGA Control
DP_EN           out34Power control
EN_12V          out114Power control
EN_3.3V         out112Power control
EN_A_3V3        out143Power control
EN_AF_1V8       out110Power control
EN_B_3V3        out74Power control
EN_BC_1V8       out84Power control
EN_C_3V3        out76Power control
EN_D_3V3        out78Power control
EN_DE_1V8       out77Power control
EN_E_3V3        out82Power control
EN_F_3V3        out104Power control
EN_GT_L         out122Power control
EN_GT_R         out125Power control
EN_SFP          out111Power control
EN_SFP_SSD      out3Power control
EN_VCCINT       out119Power control
FAN_A_EN        out106Fan control
FAN_B_EN        out83Fan control
FAN_C_EN        out81Fan control
FAN_D_EN        out75Fan control
FAN_E_EN        out73Fan control
FAN_F_EN        out109Fan control
FMC12V_EN/EN_FMC_12Vout95Power control
FMC12V_PG        93Power control / currently_not_used
FMCA_PG_C2M      142Power control / currently_not_used 
FMCA_PG_M2C      141Power control / currently_not_used
FMCA_PRSNT      in140FMC
FMCA_TCK        out139FMC / JTAG
FMCA_TDI        out138FMC / JTAG
FMCA_TDO        in133FMC / JTAG
FMCA_TMS        out132FMC / JTAG
FMCB_PG_C2M      38FMC / currently_not_used
FMCB_PG_M2C      39FMC / currently_not_used
FMCB_PRSNT      in40FMC
FMCB_TCK        out41FMC / JTAG
FMCB_TDI        out42FMC / JTAG
FMCB_TDO        in43FMC / JTAG
FMCB_TMS        out44FMC / JTAG
FMCC_PG_C2M      54FMC / currently_not_used
FMCC_PG_M2C      55FMC / currently_not_used
FMCC_PRSNT      in56FMC
FMCC_TCK        out57FMC / JTAG
FMCC_TDI        out58FMC / JTAG
FMCC_TDO        in59FMC / JTAG
FMCC_TMS        out60FMC / JTAG
FMCD_PG_C2M      45FMC / currently_not_used
FMCD_PG_M2C      47FMC / currently_not_used
FMCD_PRSNT      in61FMC
FMCD_TCK        out48FMC / JTAG
FMCD_TDI        out49FMC / JTAG
FMCD_TDO        in50FMC / JTAG
FMCD_TMS        out52FMC / JTAG
FMCE_PG_C2M      62FMC / currently_not_used
FMCE_PG_M2C      65FMC / currently_not_used
FMCE_PRSNT      in67FMC
FMCE_TCK        out68FMC / JTAG
FMCE_TDI        out69FMC / JTAG
FMCE_TDO        in70FMC / JTAG
FMCE_TMS        out71FMC / JTAG
FMCF_PG_C2M      107FMC / currently_not_used
FMCF_PG_M2C      105FMC / currently_not_used
FMCF_PRSNT      in100FMC
FMCF_TCK        out99FMC / JTAG
FMCF_TDI        out98FMC / JTAG
FMCF_TDO        in97FMC / JTAG
FMCF_TMS        out96FMC / JTAG
INIT_B          in5FPGA Control
JTAGENB--120enable JTAG access to CPLD (one CPLD, zero FMC chain)
MIO24            1FGPA MIO / currently_not_used
MIO25            2FGPA MIO / currently_not_used
MODE0           out10FPGA Boot Mode
MODE1           out12FPGA Boot Mode
MODE2           out9FPGA Boot Mode
MODE3           out11FPGA Boot Mode
MR              out92FPGA Control
PG_12V          in113Power control
PG_FPD           in115Power control / currently_not_usedcontrol 
PG_GT_L         in13Power control
PG_GT_R         in35Power control
PG_PSGT         in128Power control
PROG_B          out6FPGA Control
PSGT_EN/EN_GT_PS        out117Power control
SC_IO0          out25Slave CPLD / Reset
SC_IO1           26Slave CPLD / currently_not_used
SC_IO2           27Slave CPLD / currently_not_used
SC_IO3          in28Slave CPLD / Slave RGPIO TX_IN 
SC_IO4          out32Slave CPLD / Slave RGPIO RX_OUT
SC_IO5          out33Slave CPLD / Slave RGPIO CLK_out
SC_SW1          in127DIP Switch S3-3
SC_SW2          in85DIP Switch S3-4
SC1_IO_SB        91Slave CPLD /  currently_not_used
SC2_IO_SB        86Slave CPLD /  currently_not_used
USR_BUT2        in94Button / Global Reset

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JTAGENB set CPLD into the Chain for Firmware update. In normal mode every FMC JTAG will be set into the chain, when his FMCx_PRSNT is detected.

Power

All power ENN_12V and EN_VCCINT are enabled. All other powers will be enabled without sequencingif, PG_12V and PG_FPD are valid.

Reset

PROG_B always one. MR and SC_IO0 controlled by USR_BUT2 (S2) and power management.

Bootmode

SD Boot, when SC_SW1 is one else SQPI Boot.

S4-3S4-5Description
OFFOFFSD1 Boot
OFFONPJTAG0
ONOFFQSPI32
ONONJTAG

 

FANs 

6 FMC FANs controlled by corresponding FMCx_PRSNT signals to enable FANs only for active FMC slots.

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Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV04 to REV05

  • more Boot Modes selectable
  • Power startup sequence

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

2016-10-16
DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription
2017.05.23

Page info
current-version
current-version
prefixv.

 

REV02REV01

Page info
modified-users
modified-users

REV02 working in process
2016-10-16

 

 

v.22

REV01REV01

Page info
modified-users
modified-users

Revision 01 finished
2016-04-11

 

v.1

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Page info
created-user
created-user

Initial release
 All  
 

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