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Refer to https://shopwiki.trenz-electronic.de/ee/Download/?path=Trenz_Electronicdisplay/PD/TE0841+TRM for downloadableonline version of this manual and additional technical documentation of the product.
 

The Trenz Electronic TE0841-01 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale KU035 FPGA, 2 banks of 512 MByte DDR4 SDRAM, 32 MByte QSPI Flash for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

Key Features

  • Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
  • 2 banks of 512 MByte, 16 bit wide DDR4 SDRAM
  • 256 Mbit (32 MByte) QSPI Flash
  • 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
    - User I/O: 60 x HR, 84 x HP
    - Serial transceiver: 8 x GTH lanes (TX/RX)
    - GT clock inputs: 2
  • Clocking
    - Si5338 - 4 output PLLs, GT and PL clocks
    - 200 MHz LVDS oscillator
  • All power supplies on-board, single power source operation
  • Evenly spread supply pins for optimized signal integrity
  • Size: 40 x 50 mm
  • 3 mm mounting holes for skyline heat spreader
  • Rugged for industrial applications

Additional assembly options for cost or performance optimization plus high volume prices are available on request.

Block Diagram

Main Components

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  1. Xilinx Kintex UltraScale FPGA, U1
  2. Ultra Performance Oscillator performance oscillator @25.000000 MHz, U3
  3. 12A PowerSoC DC-DC Converter converter (0.95V), U14
  4. 12A PowerSoC DC-DC Converter converter (0.95V), U7
  5. Low-jitter Precision precision LVDS Oscillator oscillator @200.0000 MHz, U11
  6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
  7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
  8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  11. Programmable quad clock generator, U2
  12. 32 MByte QSPI Flash, U6
  13. 4 Gbit DDR4 SDRAM, U4
  14. 4 Gbit DDR4 SDRAM, U5
  15. System Controller CPLD, U18
  16. Low-dropout (LDO) linear regulator (MGTAUX), U9
  17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Key Features

  • Xilinx Kintex UltraScale XCKU035 FPGA
  • Rugged for industrial applications
  • 2 banks of 512 MByte, 16 bit wide DDR4 SDRAM
  • 256 Mbit (32 MByte) QSPI Flash
  • Size: 40 x 50 mm
  • 3 mm mounting holes for skyline heat spreader
  • B2B Connectors: 3 x Samtec Razor Beam LSHM, 260 terminals total
    - User I/O: 12 x HR, 132 x HP
    - Serial transceiver: 8 x GTH lanes (TX/RX)
    - GT clock inputs: 2
  • Clocking
    - Si5338 - 4 output PLLs, GT and PL clocks
    - 200 MHz LVDS oscillator
  • All power supplies on-board, single power source operation
  • Evenly spread supply pins for optimized signal integrity

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Initial Delivery State

Storage device name

Content

Notes

OTP Flash area

Empty

 

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltageNotes
64HRJM148 IOs, 24 LVDS pairsB64_VCCOSupplied by the baseboardcarrier board.
65HRJM18 IOs3.3V 
224MGTJM13 lanes  
65HRJM34 IOs, 2 LVDS pairs3.3V 
66HPJM316 IOs, 8 LVDS pairsB66_VCCOSupplied by the baseboardcarrier board
224MGTJM31 lane  
225MGTJM34 lanes  
67HPJM248 IOs, 24 LVDS pairsB67_VCCOSupplied by the baseboardcarrier board
67HPJM22 IOsB67_VCCOSupplied by the baseboardcarrier board
68HPJM218 IOs, 9 LVDS pairsB68_VCCOSupplied by the baseboardcarrier board

For detailed information about the pin out, please refer to the Pin-out Tables. 

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Clock SignalFrequencySourceFPGANotes
-

25.000000 MHz

SiT8208 (U3), CLK-Reference clock input for Si5338 PLL quad clock generator.
CLK200M200.0000 MHzDSC1123 (U11), OUTR25/R26, bank 45 
CLK0User programmableSi5338 (U2), CLK3T24/T25, bank 45 
CLK1User programmableSi5338 (U2), CLK0R23/P23, bank 45 
MGT_CLK0Baseboard suppliedSupplied by the carrier boardJM3-31, JM3-33Y5/Y6, bank 225Bank 225 MGTs clock source from baseboard.
MGT_CLK1User programmableSi5338 (U2), CLK1V5/V6, bank 225Bank 225 MGTs clock source from on-board PLL quad clock generator.
MGT_CLK2Baseboard suppliedSupplied by the carrier boardJM3-32, JM3-34AD6/AD5, bank 224Bank 224 MGTs clock source from baseboard.
MGT_CLK3User programmableSi5338 (U2), CLK2AB6/AB5, bank 224Bank 224 MGTs clock source from on-board PLL quad clock generator.

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Power Consumption

Power Input PinMax Typical Current
VINTBD*
3.3VINTBD*

 * TBD - To be determined soon with reference design setup.

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For highest efficiency of the on-board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See also Xilinx datasheet DS892 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0720 module.

Power Rails

Voltages on B2B

Connectors

B2B JM1 Pins

B2B JM2 Pins

Input/Output

Notes
VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
B64_VCO9, 11-InputHR (High Range) bank voltage.
B66_VCO-1, 3InputHP (High Performance) bank voltage.
B67_VCO-7, 9InputHP (High Performance) bank voltage.
B68_VCO-5InputHP (High Performance) bank voltage.

VBAT_IN

79-InputRTC battery supply voltage.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage level.

Board to Board Connectors

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Variants Currently In Production

Module Variant

FPGA Chip

PL Clock
Temperature Range
TE0841-01-035-1CXCKU035-1SFVA784C
 
Commercial
TE0841-01-035-1I
XCKU035-1SFVA784I
 
Industrial
TE0841-01-035-2I
XCKU035-2SFVA784I
 
Industrial
TE0841-01-040-1CXCKU040-1SFVA784CCommercial
TE0841-01-040-1IXCKU040-1SFVA784IIndustrial

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

  

V

-
Supply voltage for HR I/O banks (VCCO)
–0.500
3.400
VSee Xilinx datasheet DS892.
Supply voltage for HP I/O banks (VCCO)
–0.500
2.000VSee Xilinx datasheet DS892.
I/O input voltage for HR I/O banks
–0.400
VCCO + 0.550
VSee Xilinx datasheet DS892.
I/O input voltage for HP I/O banks
–0.550
VCCO + 0.550
VSee Xilinx datasheet DS892.
GTH and GTY transceivers receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage
-0.500
1.260
VSee Xilinx datasheet DS892.

Storage temperature

-40

+85

°C

-

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage    
Supply voltage for HR I/O banks (VCCO)1.140
3.400
VSee Xilinx datasheet DS892.
Supply voltage for HP I/O banks (VCCO)
0.950
1.890
VSee Xilinx datasheet DS892.
I/O input voltage
–0.200
VCCO + 0.20VSee Xilinx datasheet DS892.
Note
Assembly variants for higher storage temperature range are available on request.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

  • PCB thickness: 1.6 mm.

  • Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

   

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

47 g - Plain module.

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Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2015-12-09

01

First production revision

-TE0841-01

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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Date

Revision

Contributors

Description

2017-0106-3112
Jan Kumann
Initial document.

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