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| Name / opt. VHD Name | Direction | Pin | Description |
|---|---|---|---|
| C_TCK | in | 30 | JTAG B2B |
| C_TDI | in | 32 | JTAG B2B |
| C_TDO | out | 1 | JTAG B2B |
| C_TMS | in | 29 | JTAG B2B |
| EN1 | in | 27 | Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback |
| ERR_OUT | in | 4 | PS_ERROR_OUT, see ug1085 |
| ERR_STATUS | in | 5 | PS_ERROR_STATUS, see ug1085 / currently_not_used |
| JTAGEN | in | 26 | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
| MODE | in | 25 | Boot Mode for Zynq/ZynqMP Devices (Flash or SD) |
| MODE0 | out | 12 | ZynqMP Boot Mode Pin 0 |
| MODE1 | out | 13 | ZynqMP Boot Mode Pin 1 |
| MODE2 | out | 14 | ZynqMP Boot Mode Pin 2 |
| MODE3 | out | 16 | ZynqMP Boot Mode Pin 3 |
| NOSEQ | inout | 23 | / currently_not_used |
| PGOOD | out | 28 | Module Power Good. |
| PHY_LED1 | in | 17 | ETH PHY LED1 |
| TCK | out | 9 | JTAG ZynqMP |
| TDI | out | 8 | JTAG ZynqMP |
| TDO | in | 10 | JTAG ZynqMP |
| TMS | out | 11 | JTAG ZynqMP |
| X0 | out | 20 | FPGA IO / PHY_LED1 |
| X1 | out | 21 | FPGA IO / Firmware Variant |
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PGOOD is EN1 and not ER_OUT. There is no additional power management controlled by CPLD.
Internal pullup is used for detection, ER_OUT IO powered by 1.8V. To detect power status, also B2B 1.8V or 3.3V output is usable.
X0/X1 Pin
| Pin | Description |
|---|---|
| X0 | PHY_LED1 |
| X1 | Firmware Variant: 0 SD boot, 1: QSPI |
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Overview
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