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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.
Boot Mode
2 Boot Modes can be selected via B2B Pin Mode. For other options Firmware update is necessary. At the moment JTAG Mode is needed to write QSPI Flash with Xilinx Tools. Trenz Electronic provides currently 2 Firmware variants, one for SD and one for QSPI usage.
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For other UltraScale+ Boot Modes options custom firmware is needed, see also Table 11.1 Boot Modes from Xilinx UG1085.
| Note |
|---|
Set Boot Mode to JTAG, to write boot image to QSPI with Xilinx tools (Vivado or SDK). |
Power
PGOOD is EN1 and not ER_OUT. There is no additional power management controlled by CPLD.
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| Pin | Description |
|---|---|
| X0 | PHY_LED1 |
| X1 | Firmware Variant: 0 SD boot, 1: QSPI |
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Appx. A: Change History
Revision Changes
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV02 | REV02, REV01, REV02 |
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| 2017-08-17 | v.8 | REV02 | REV02, REV01 | John Hartfiel |
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| 2017-06-08 | v.4 | REV01 | REV01 | John Hartfiel |
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| 2017-03-06 | v.2 | REV01 | REV01 | John Hartfiel |
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| 2017-03-06 | v.1 | REV01 | REV01 |
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| All |
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Overview
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